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Observer
Observer
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Registered: ‎06-14-2018

CLK error place

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Hi,

I'm using the Artix7 part number: xc7a100tcsg324-2 and got this error:

[Place 30-602] IO port 'ref_clk' is driving multiple buffers. This will lead to unplaceable/unroutable situation.
The buffers connected are:
ad_ibox_pll_top/pix_clk_pll/inst/clkin1_ibufg {IBUF}
ad_ibox_pll_top/main_pll/inst/clkin1_ibufg {IBUF}

 

Than I placed a BUFG between the input to the DUT and the input to these PLLs.
It gave me a different error about the resources of the Artix-7.
What am I doing wrong?

 

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498 Views
Registered: ‎01-22-2015

@michaelsterin 

It looks like you are trying to route a clock from the IO pin, refclk, to two PLLs called pix_clk_pll and main_pll.  It also seems that you told the Clocking Wizard for each PLL that the "Source" is a “Single ended clock capable pin”.   This will cause problems.

Try the following:  
Route the clock from the refclk pin to a BUFG and from the BUFG to the two PLLs.  Then, in the Clocking Wizard for each PLL, specify that the PLL "Source" is “No buffer”.
PLL_input_no_buffer.jpg

When adding the BUFG as I described, you also need to add constraints for refclk to the Vivado .xdc constraints file that look something like the following:

create_clock -period X.XXX [get_ports refclk]
set_input_jitter [get_clocks -of_objects [get_ports refclk]] Y.YY
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {refclk_IBUF_inst/O}]

where X.XXX is the period (ns) of refclk and Y.YY is the jitter (ns Pk-Pk) of refclk.

Mark

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Moderator
Moderator
669 Views
Registered: ‎01-16-2013

@michaelsterin 

 

Can you open the synthesized design and show the schematic of the buffers mentioned in error message with connection. 

Also check this forum thread:

https://forums.xilinx.com/t5/Processor-System-Design/Differential-input-clock-driving-to-multiple-IBUFDS/td-p/438748 

 

--Syed

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Observer
Observer
531 Views
Registered: ‎06-14-2018

Hi,

It looks that I'm using the wrong port for the ref_clk.

Is there any dedicated port that I should use for the reference clock in this device?

If yes, please let me know some options for that.

Thx

Neta

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Moderator
Moderator
510 Views
Registered: ‎05-08-2012

Hi @michaelsterin 

The original error looks to show the design connecting one port to two IBUFs. This is not possible, as there is one physical path to one IBUF. I would suggest opening the elaborated design to see which IBUF buffer can be removed.

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Highlighted
499 Views
Registered: ‎01-22-2015

@michaelsterin 

It looks like you are trying to route a clock from the IO pin, refclk, to two PLLs called pix_clk_pll and main_pll.  It also seems that you told the Clocking Wizard for each PLL that the "Source" is a “Single ended clock capable pin”.   This will cause problems.

Try the following:  
Route the clock from the refclk pin to a BUFG and from the BUFG to the two PLLs.  Then, in the Clocking Wizard for each PLL, specify that the PLL "Source" is “No buffer”.
PLL_input_no_buffer.jpg

When adding the BUFG as I described, you also need to add constraints for refclk to the Vivado .xdc constraints file that look something like the following:

create_clock -period X.XXX [get_ports refclk]
set_input_jitter [get_clocks -of_objects [get_ports refclk]] Y.YY
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {refclk_IBUF_inst/O}]

where X.XXX is the period (ns) of refclk and Y.YY is the jitter (ns Pk-Pk) of refclk.

Mark

View solution in original post

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Observer
Observer
434 Views
Registered: ‎06-14-2018

Great thx,

 

Issue solved.

 

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