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Visitor regank33
Visitor
4,608 Views
Registered: ‎12-25-2013

CLK to data confusing constraints

I have a problem which I do not understand.

 

Background / what I'm trying to do:

I'm using a spartan 6 PN: XC6SLX16-3CSG324I

 

I'm using a differential LVDS clock input from 0.05 to 500 MHz on BANK0 and BANK2 to generate 16 channels on each bank at 0.1 to 1 Gbps with 9 selectable different PRBS patterns. All 16 channels must have minimal skew between them.

 

The two clocks are corrolated, but have different phase between them.

 

Internally in the FPGA, each clock drives four BUFIO2_CLK instances for each 16 channels.

 

One DIVCLK (divide = 8) is used from one of the BUIO2_CLK instances to drive a DCM_SP instance. Output clk from DCM is distributed on the dedicated clock lines to provide a system clock from 0.0125 to 125 MHz .

 

Each GCLK in each bank drives 9 different PRBS generators with each PRBS generator having 128 channels to drive 16,  8:1 OSERDES (DDR MODE).

 

I have tried various constraints and numerious Process properties and have failed.

 

A global reset routed to dedicated clock lines have been used to Clear/Set all PRBS generators and OSERDES blocks.

 

Sometimes the design works. Sometimes it does not after reprogramming the FPGA. 

I have seen ghosting on a single 1Gbps channel with a PRBS7 pattern visible, but with errors.

The amount of errors will vary from changing the input clock frequency. This has led me to the conclusion that not all 8 data channel going into the 8:1 OSERDES block are aligned.

 

How would I go about constraining all 128 PRBS channels for each of the 9 PRBS generators through a big 9 by 128 selector then to all 16, 8:1 OSERDES to be all aligned to the IOCLK, SerdesStrobe and GCLK ?

 

I can send all files upon request. thank you for reading

 

 

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