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Newbie nico_b_100
Newbie
4,323 Views
Registered: ‎07-02-2012

CLOCK_DEDICATED_ROUTE does not work with cascaded BUFGs

Hallo,

 

I‘ve got the following problem:

 

In short:

  • If cascading some bufg’s and bufgctrl, I get the message “ERROR:Place:1131 - Unroutable Placement! …”.
  • Using the option “… CLOCK_DEDICATED_ROUTE=FALSE;” does not work with the ISE 13.4 (lin64) for a Virtex6.

 

In detail:

I’ve reduced a bigger design to the following example.

  • 2 input clocks “i_clk_<p|n>” – go into one “bufg” each with the 2 resulting output/signals “clk_<p|n>”
  • Than one of these signals “clk_<p|n>” is selected by the “bufgctrl” (asynchronous) with the resulting output/signal “selected_clk_pos_nneg”
  • Finally, the signal “selected_clk_pos_nneg” goes to another “bufg” with the resulting output “o_clk_out”

Remark: in this example some bufg’s could be removed, however in the original design not.

 

Code:

library IEEE;

  use IEEE.STD_LOGIC_1164.ALL;

 

library UNISIM;

  use UNISIM.VComponents.all;

 

 

entity bufg_test is

    PORT(

        i_clk_p   : in  std_logic;

        i_clk_n   : in  std_logic;

                                 sel_clk_p : in  std_logic;

 

        o_clk_out : out std_logic

    );

 

end bufg_test;

 

 

architecture structural of bufg_test is

 

    COMPONENT BUFG

        port(

            I : in  std_ulogic;

            O : out std_ulogic

        );

    END COMPONENT;

 

    COMPONENT BUFGCTRL

        generic(

            INIT_OUT     : integer := 0;

            PRESELECT_I0 : boolean := false;

            PRESELECT_I1 : boolean := false

        );

        port(

            CE0                            : in  std_ulogic;

            CE1                            : in  std_ulogic;

            I0                      : in  std_ulogic;

            I1       : in  std_ulogic;

            IGNORE0 : in  std_ulogic;

            IGNORE1 : in  std_ulogic;

            S0                                 : in  std_ulogic;

            S1                     : in  std_ulogic;

            O                                   : out std_ulogic

    );

    END COMPONENT;

 

 

    SIGNAL logic_1 : std_logic;

 

    SIGNAL clk_p : std_logic;

    SIGNAL clk_n : std_logic;

    SIGNAL sel_clk_n : std_logic;

 

    SIGNAL selected_clk_pos_nneg : std_logic;

 

begin

 

    logic_1   <= '1';

    sel_clk_n <= NOT sel_clk_p;

 

    i_bufg_x1_p : BUFG

        PORT MAP(

            I => i_clk_p,

            O => clk_p

        );

 

    i_bufg_x1_n : BUFG

        PORT MAP(

            I => i_clk_n,

            O => clk_n

        );

 

    i_bufg_select_x1_p_or_n : BUFGCTRL

        PORT MAP(

            CE0     => logic_1,

            CE1     => logic_1,

            I0      => clk_p,

            I1      => clk_n,

            IGNORE0 => logic_1,

            IGNORE1 => logic_1,

            S0      => sel_clk_p,

            S1      => sel_clk_n,

            O       => selected_clk_pos_nneg

        );

 

    i_bufg_post_selection : BUFG

        PORT MAP(

            I => selected_clk_pos_nneg,

            O => o_clk_out

        );

 

end structural;

 

 

Virtex6 Restriction:

Due to the cascading restriction of bufg’s (UG 362 Clocking Ressources, Figure 1-3 Cascading BUFGs), one bufg may drive only the input of its direct neighbors. If looking to the above mentioned example, indeed there is no way for P&R to do such routing. Therefore, the tool is right with the following error:

                                    

 

“Section 1 - Errors

------------------

ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component

   pair have been found that are not placed at a routable site pair. The driver

   BUFGCTRL component <i_bufg_x1_n> is placed at site <BUFGCTRL_X0Y18>. The load

   BUFGCTRL component <i_bufg_select_x1_p_or_n> is placed at site

   <BUFGCTRL_X0Y9>. The BUFGCTRL components can use the fast path between them

   if they are placed in adjacent BUFGCTRL sites, and both are in the same half

   of the device (TOP or BOTTOM). You may want to analyze why this problem

   exists and correct it. This placement is UNROUTABLE in PAR and therefore,

   this error condition should be fixed in your design. You may use the

   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a

   WARNING in order to generate an NCD file. This NCD file can then be used in

   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this

   clock placement rule is listed below. These examples can be used directly in

   the .ucf file to demote this ERROR to a WARNING.

 

Phase 5.2  Initial Placement for Architecture Specific Features

(Checksum:3e111235) REAL time: 50 secs

 

Total REAL time to Placer completion: 50 secs

Total CPU  time to Placer completion: 49 secs

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.”

 

 

Problem:

1)

if using in the *.ucf file:

PIN "i_bufg_x1_p.O" CLOCK_DEDICATED_ROUTE=FALSE;

PIN "i_bufg_x1_n.O" CLOCK_DEDICATED_ROUTE=FALSE;

PIN "i_bufg_select_x1_p_or_n.O" CLOCK_DEDICATED_ROUTE=FALSE;

or even

PIN "*bufg*.O" CLOCK_DEDICATED_ROUTE=FALSE;

the constraints are ignored and the errors stays the same.

 

2)

In the error message the tool says “… A list of all the COMP.PINS used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to demote this ERROR to a WARNING.”. Unfortunately, there is no such list in the error message or in any other log file.

 

Do you know a way to let the tool not use the dedicated clock route via a global net?

 

Thank you very much!

Best Regards

Nico

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1 Reply
Xilinx Employee
Xilinx Employee
4,311 Views
Registered: ‎07-01-2008

Re: CLOCK_DEDICATED_ROUTE does not work with cascaded BUFGs

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