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10,203 Views
Registered: ‎01-22-2015

CLOCK_DEDICATED_ROUTE property

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Working in Vivado 2016.4, I use the following circuit for source-synchronous SDR input to the FPGA.

 

SSI2_FPGA_IO_B.jpg

As the circuit shows, a single-ended forwarded clock, SSI2_CLK, is routed directly from the SSI2_CLK pin/port into an MMCM. However, implementation throws the following error,

 

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair….

 

..and mentions (but discourages) use of the following constraint to solve the error.

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets MMCM2/inst/CLK_IN1_CLK_GEN2]

 

Use of the constraint solves the error but implementation physically places the MMCM far away from the SSI2_CLK pin. Device view shows an unused MMCM located right beside SSI2_CLK pin. 

 

Why isn’t implementation using the (unused) MMCM located beside the SSI2_CLK pin?

 

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Scholar austin
Scholar
14,904 Views
Registered: ‎02-27-2008

Re: CLOCK_DEDICATED_ROUTE property

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m,

 

Is the clock coming in on a clock capable IO pin?

 

What timing constraints are applied to the data input, and the clock?

Austin Lesea
Principal Engineer
Xilinx San Jose
14 Replies
Scholar austin
Scholar
14,905 Views
Registered: ‎02-27-2008

Re: CLOCK_DEDICATED_ROUTE property

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m,

 

Is the clock coming in on a clock capable IO pin?

 

What timing constraints are applied to the data input, and the clock?

Austin Lesea
Principal Engineer
Xilinx San Jose
Voyager
Voyager
10,187 Views
Registered: ‎06-24-2013

Re: CLOCK_DEDICATED_ROUTE property

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Why isn’t implementation using the (unused) MMCM located beside the SSI2_CLK pin?

 

Because you told Vivado that the path from the SSI2_CLK pin doesn't matter :)

 

Best,

Herbert

-------------- Yes, I do this for fun!
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Historian
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10,173 Views
Registered: ‎01-23-2009

Re: CLOCK_DEDICATED_ROUTE property

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As @austin asked - is the clock coming in on a clock capable (CC) input. If not, then the using the CLOCK_DEDICATED_ROUTE = FALSE allows the tool to make the connection, but it has to do so using fabric logic.

 

For the clocking stuff, "close" has no meaning. The routing to the inputs of the MMCM have dedicated paths from a variety of places. If you are not using the ones directly from the CC pins, then (I think) it needs to come from the global input area, which is in the center of the die. So, your non-clock capable pin is routed to the center of the die using fabric routing, and from there routed to the MMCM - the fact that they are not physically close to each other doesn't make this any better or worse.

 

Of course, the timing of this sub-optimal clock input is going to be significantly worse than if the clock came from a CC pin. If you can still meet timing with this sub-optimal placement (assuming your input constraints are completely accurate, including board delay, duty cycle error, clock jitter, etc...), then your design is fine like this; the timing may change from run-to-run, but if it meets timing it is OK. In general, this won't be the case for faster interfaces (you don't tell us how fast SSI2_CLK is running).

 

Lastly, are you forcing the flip-flop into the IOB? Timing is more predictable (and better) if the capture flip-flop is in the IOB. Do this with

 

set_property IOB TRUE [get_ports SSI2_DAT]

 

Avrum

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10,159 Views
Registered: ‎06-24-2013

Re: CLOCK_DEDICATED_ROUTE property

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@austin, @avrumw

 

From the fact that Vivado reports:

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair….

 

I would conclude that the clock is comming in on a clock-capable input.

Is that conclusion wrong?

 

Thanks,

Herbert

-------------- Yes, I do this for fun!
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Historian
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10,154 Views
Registered: ‎01-23-2009

Re: CLOCK_DEDICATED_ROUTE property

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@hpoetzl

 

I would conclude that the clock is comming in on a clock-capable input.

Is that conclusion wrong?

 

It certainly seems to imply that the clock is coming in on a clock capable I/O.

 

If that is the case, the I can think of three reasons why this could be happening:

 

1) The MMCM is being LOC'ed to a location other than the one in the same clock region, This would actually have to be a user entered LOC constraint. If the MMCM has no LOC constraint (and condition 2 and 3 below doesn't exist), then the tools will automatically place the MMCM in the same clock region as the clock capable I/O

 

2) The MMCM in the clock region is already used. There are 4 clock capable I/Os in a clock region. If more than one of them tries to use an MMCM, then only one of them can succeed with the "dedicated" route (since there is only one MMCM per clock region), and the other will get this message.

 

3) The same clock input is being used to drive 2 MMCMs. Again, only one MMCM per clock region exists...

 

If it is case #1, then just remove the LOC constraint.

 

If it is case #2 or #3, then you have a couple of choices

  a) Use a PLL instead of an MMCM for one of the two clocks. For simple deskewing the PLL has the same capabilities as the MMCM (it actually can be the preferred choice since it can have less output jitter). So one clock will use the MMCM and the other will use the PLL in the same region

  b) Use the MMCM in an adjacent region. Set CLOCK_DEDICATED_ROUTE = BACKBONE to allow the tools to use the dedicated connection to the MMCM in the region above or below the clock capable pin. This implementation does introduce some skew into the clock, but nowhere near as much as option c)

   c) Use another MMCM somewhere else in the die. Set CLOCK_DEDICATED_ROUTE = FALSE

 

Avrum

10,141 Views
Registered: ‎01-22-2015

Re: CLOCK_DEDICATED_ROUTE property

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@austin - you are correct!!   I was bringing in the clock thru a pin that was not clock capable.

 

I now bring the clock in thru a clock capable pin and (as suggested by Avrum) place the capture flop in the IOB.  I no longer need to set the CLOCK_DEDICATED_ROUTE property, I no longer get the implementation error, and the MMCM located beside the clock capable pin is being used.

 

Finally, if I understand Avrum correctly, there is only one MMCM in each clock-region and this is the MMCM that "Device View" shows me to be located right beside by clock capable pin.  So, with implementation now using the "preferred" MMCM (and assuming no more mistakes by me),  I needn't worry that future implementations will use some other MMCM in the FPGA?

 

 

 

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Historian
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10,137 Views
Registered: ‎01-23-2009

Re: CLOCK_DEDICATED_ROUTE property

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So, with implementation now using the "preferred" MMCM (and assuming no more mistakes by me),  I needn't worry that future implementations will use some other MMCM in the FPGA?

 

Yes. The tools have an implicit rule to use the MMCM in the same clock region as a clock capable pin whenever possible.

 

Avrum

Voyager
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10,134 Views
Registered: ‎06-24-2013

Re: CLOCK_DEDICATED_ROUTE property

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markg@prosensing.com you are correct!!   I was bringing in the clock thru a pin that was not clock capable. 

 

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair….

 

So who do be blame here, the tools or you?

Let's just say Vivado doesn't know what a clock capable pin is  ...

 

Best,

Herbert

-------------- Yes, I do this for fun!
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10,089 Views
Registered: ‎01-22-2015

Re: CLOCK_DEDICATED_ROUTE property

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Thanks Avrum!

 

Assuming that my board is already made - ugh - is there a way to bring my forwarded clock from a pin that is not clock capable into the MMCM?

 

Mark

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7,274 Views
Registered: ‎06-24-2013

Re: CLOCK_DEDICATED_ROUTE property

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Hey markg@prosensing.com

 

is there a way to bring my forwarded clock from a pin that is not clock capable into the MMCM?

Basically any fabric signal, including the input from your non-clock-capable pin can be used to drive the MMCM or PLL.

Just remember that the tools will warn and the timing will be sub-optimal.

 

Best,

Herbert

-------------- Yes, I do this for fun!
Scholar austin
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7,263 Views
Registered: ‎02-27-2008

Re: CLOCK_DEDICATED_ROUTE property

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And ...

 

There will be an increase in system jitter on this clock of about 10-20%.  So if system jitter on a CC pin clock is 100 ps, it will be perhaps 120 ps P-P on a non-CC pin.  Just set_system_jitter to a 20% larger value than what you have been using.  If you haven't set it at all (using default), you should measure the system jitter, then use that value to implement your design.

 

At that point, the result is guaranteed (timing is met) if slack is > 0.

Austin Lesea
Principal Engineer
Xilinx San Jose
Historian
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7,258 Views
Registered: ‎01-23-2009

Re: CLOCK_DEDICATED_ROUTE property

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And, as the warning message says, you need to set CLOCK_DEDICATED_ROUTE FALSE on the net between the IBUF and the MMCM.

 

Avrum

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7,250 Views
Registered: ‎01-22-2015

Re: CLOCK_DEDICATED_ROUTE property

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Austin, Avrum, and Herbert  - thanks for much information and for the rescue!

 

Mark

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Voyager
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7,246 Views
Registered: ‎06-24-2013

Re: CLOCK_DEDICATED_ROUTE property

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You're welcome!

Best,
Herbert
-------------- Yes, I do this for fun!
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