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Explorer
Explorer
487 Views
Registered: ‎06-08-2017

CRITICAL WARNING: [Route 35-162] signals failed to route due to routing congestion.

I am using the hierarchical design flow from UG946 to implement some of my design modules out-of-context.

I get the error in the title because two of the OOC modules used some of the same routing resources. Here's some relevant parts from the attached log file.

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 4534
 Number of Nodes with overlaps = 658
 Number of Nodes with overlaps = 95
 Number of Nodes with overlaps = 22
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 2
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.522  | TNS=0.000  | WHS=N/A    | THS=N/A    |

WARNING: [Route 35-447] Congestion is preventing the router from routing all nets. The router will prioritize the successful completion of routing all nets over timing optimizations.
Phase 4.1 Global Iteration 0 | Checksum: 2a3a30023

Phase 9 Verifying routed nets
CRITICAL WARNING: [Route 35-162] 2 signals failed to route due to routing congestion. Please run report_route_status to get a full summary of the design's routing.
Below is a list of the top 10 physical nodes with signal overlaps and up to 5 of the signals that were contending for this node resource:
Resolution: Run report_route_status to get a full summary of the design's routing. To find the areas of the congestion, use the route congestion Metrics in the Device View and check the logfile for the Congestion Report.
1. Tile Name: INT_L_X4Y123 Node: SE6BEG0 Overlapping Nets: 2
SR_CTRL0/SR_IN
sDACinst/sDAC_SDO

Is there a way to prevent this from happening with OOC modules? This pretty much negates OOC implementation unless it can be prevented. I've attached some log file. I tried to attach the routed DCPs for each module and the full design with the conflicing route, but the site wouldn't let me attach?

Thank you four the help.

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2 Replies
Xilinx Employee
Xilinx Employee
467 Views
Registered: ‎05-08-2012

Re: CRITICAL WARNING: [Route 35-162] signals failed to route due to routing congestion.

Hi @dschussheim 

Is the OOC implementation not expected to be congested based on the report_utilization and report_design_analysis -congestion? There are a few resources that can help in resolving congestion such as the UltraFast Methodology Guide, and the below answer record.

https://www.xilinx.com/support/answers/66314.html


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Explorer
Explorer
433 Views
Registered: ‎06-08-2017

Re: CRITICAL WARNING: [Route 35-162] signals failed to route due to routing congestion.

Thanks for your reply.

Based on those reports, the OOC designs are not expected to be congested.

The issue was that one OOC module has connections to IO pads, and the routing to one of the pads passes through the PBLOCK of the other OOC module. There was a conflict because the two signals overlapped in the final top implementation that includes all OOC modules.

I was able to "solve" this issue by reimplementing one of the OOC modules with a different directive. This moved the conflicting signal to another interconnect. 

I guess this post describes what I'd like to do with my design.

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