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Explorer
Explorer
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Registered: ‎03-18-2008

CRITICAL WARNING: [Vivado 12-1411] by vivado2017.3

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CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Terminal rst_n cannot be placed on L19 (IOB_X1Y753) because the pad is already occupied by terminal sgmii_phy_rst possibly due to user constraint [E:/temp/fpga/constrain/top.xdc:15]

 

set_property PACKAGE_PIN L19 [get_ports "rst_n"]
set_property IOSTANDARD LVCMOS12 [get_ports "rst_n"]

 

set_property PACKAGE_PIN BA21 [get_ports "sgmii_phy_rst"]
set_property IOSTANDARD LVCMOS18 [get_ports "sgmii_phy_rst"]

 

-----L19 and BA21 are two different location from UG1224.pdf. why to get the warning?

 

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 185 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: rst_n.

 

 

clocking.png
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Explorer
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Registered: ‎03-18-2008

Re: CRITICAL WARNING: [Vivado 12-1411] by vivado2017.3

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I simplied the  sgmii_phy_rst inside RTL code

 

assign sgmii_phy_rst=rst_n;

 

The sgmii_phy_rst is VCU118 SGMII interface,BA21.

The rst is from VCU118 Pin,L19,cpu_retset

 

this following snapshot is from ug1224.pdf

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clocking.png
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Explorer
Explorer
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Registered: ‎03-18-2008

Re: CRITICAL WARNING: [Vivado 12-1411] by vivado2017.3

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I simplied the  sgmii_phy_rst inside RTL code

 

assign sgmii_phy_rst=rst_n;

 

The sgmii_phy_rst is VCU118 SGMII interface,BA21.

The rst is from VCU118 Pin,L19,cpu_retset

 

this following snapshot is from ug1224.pdf

View solution in original post

clocking.png
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Explorer
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Registered: ‎03-18-2008

Re: CRITICAL WARNING: [Vivado 12-1411] by vivado2017.3

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the issue is solved!

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