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Visitor
Visitor
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Registered: ‎12-10-2019

Can I use the both pll in the same gtp quad in Artix7

When I use the both pll to drive different gtp_channel in the same gtp quad, vivado can not route the two output of the IBUFDS_GTE2. How to solve these problem ? Thanks.
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @simon123456 ,

By pll, are you referring Qpll or Cpll?

The QPLL can be shared by the serial transceiver channels within the same Quad, but cannot be shared by channels in other Quads.

 

Also check the below link:

https://forums.xilinx.com/t5/Other-FPGA-Architecture/2-GTP-channel-in-same-quard-but-with-different-speed/td-p/780723

Thanks,

Raj

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Visitor
Visitor
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Registered: ‎12-10-2019

The two PLLs in GTP quad can drive all the four gtp_channel, they are not cpll. I use dedicated FPGA pads to drive IBUFDS_GTE2, one set of differential clock pins drive a separate IBUFDS_GTE2. But the two output of the IBUFDS_GTE2 can not route. I found that the output of IBUFDS_GTE2 drive two net, one drives the GTREFCLK0/1 pin, and the other feed into the GTP_COMMON_X130Y179/GTP_COMMON_INTER. And the vivado tool reports the first one route failed. Why the tool not directly drives the GTREFCLK0/1 pin through the GTP_COMMON_X130Y179/GTP_COMMON_INTER, that is the result when i use one gtp_channel. Thanks.
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @simon123456 ,

Please check this AR# and let me know whether it helped:

https://www.xilinx.com/support/answers/59064.html

Thanks,

Raj

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