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Can't $initial be synthesized?

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Visitor
Posts: 9
Registered: ‎07-26-2016

Can't $initial be synthesized?

Hi

I'm learning to build a simple MIPS SoC on my Basys 3 board, and am feeling amazed to see the memory can actually be initialized by an initial block.

module memory_io #(parameter WIDTH = 8)(
   input   			clk,
   input 			memwrite,
   input	[WIDTH-1:0]     adr,
   input        [WIDTH-1:0]     writedata,
   output   reg	[WIDTH-1:0]     memdata,
   input        [WIDTH-1:0]     swu,		// memory-mapped I/O, sw refers to switches
   input        [WIDTH-1:0]     swl,
   input        [3:0]           btn,		// btn to buttons
   output   reg [3:0]           an,		// an and seg to 7-segment display
   output   reg [WIDTH-1:0]     seg,
   output   reg [WIDTH-1:0]     ldu,		// ld to LEDs
   output   reg [WIDTH-1:0]     ldl);
   
   reg  	[31:0] 		RAM [(1<<WIDTH-2)-1:0];
   wire 	[31:0] 		word;
   
//   initial
//      begin
//         $readmemh("D:/Computer/mips_8/memfile.txt", RAM, 4);
//      end
initial begin RAM[0] <= 32'h8001_002F; RAM[1] <= 32'h8002_002E; RAM[2] <= 32'h8003_002D; RAM[3] <= 32'h8004_002C; RAM[4] <= 32'h1064_0002; RAM[5] <= 32'h0022_2822; RAM[6] <= 32'h0800_0008; RAM[7] <= 32'h0022_2820; RAM[8] <= 32'hA005_fff0; RAM[9] <= 32'h0800_0009; RAM[11] <= 32'h0102_0110; end // read and write bytes from 32-bit word always @(posedge clk) if (memwrite) if (adr >= 8'hf0) case (adr) 8'hf9: an <= writedata[3:0]; 8'hf8: seg <= writedata; 8'hf1: ldu <= writedata; 8'hf0: ldl <= writedata; endcase else case (adr[1:0]) 2'b00: RAM[adr>>2][7:0] <= writedata; 2'b01: RAM[adr>>2][15:8] <= writedata; 2'b10: RAM[adr>>2][23:16] <= writedata; 2'b11: RAM[adr>>2][31:24] <= writedata; endcase assign word = RAM[adr >> 2]; always @(*) if (adr >= 8'hf0) case (adr) 8'hf4: memdata <= {4'b0000, btn}; 8'hfc: memdata <= swl; 8'hfd: memdata <= swu; endcase else case (adr[1:0]) 2'b00: memdata <= word[31:24]; 2'b01: memdata <= word[23:16]; 2'b10: memdata <= word[15:8]; 2'b11: memdata <= word[7:0]; endcase endmodule

The initial block in this code is a small program dealing with 4 arguments, say, g, h, i, and j. It compares i and j, and uses 8 LEDs (ldl) to show g + h if i ==j, and g - h if i != j.

Now the interesting thing is, this piece of code, besides being simulated correctly, can be implemented and configured into my FPGA, and the result is as expected.

Now I'm confused: can't initial be synthesized? Then how come the program in it actually enter into my hardware?

Thank you!

Visitor
Posts: 9
Registered: ‎07-26-2016

Re: Can't $initial be synthesized?

the title is a little bit mistyped. There should be no $.

Scholar
Posts: 722
Registered: ‎03-22-2016

Re: Can't $initial be synthesized?

Check out page 10 

https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_3/pg058-blk-mem-gen.pdf

 


* Henry Bucher, Baremetal Labs, Extreme Financial Engineering: btlabs.us
meminit.PNG
Visitor
Posts: 9
Registered: ‎07-26-2016

Re: Can't $initial be synthesized?

Hi, hbucher

I know memory can be initialized using a .coe file, but here I just want to clarify if initial block can also do the job.

I've been told time and time again it can't be synthesized.

Scholar
Posts: 722
Registered: ‎03-22-2016

Re: Can't $initial be synthesized?

 

Page 142

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug901-vivado-synthesis.pdf

 


* Henry Bucher, Baremetal Labs, Extreme Financial Engineering: btlabs.us
initialverilog.PNG
Scholar
Posts: 1,815
Registered: ‎04-26-2015

Re: Can't $initial be synthesized?

@cmpt_design

 

Despite university lecturers insisting that "initial values cannot be synthesized, you must include a global reset on all storage elements to ensure correct behaviour" (at least that's what they said when I went through university) the Xilinx hardware and software has always (since the XC2000, I think) been able to support initial values. The bitstream loads the SRAM configuration memory, all the flipflops (even if they're not used), and all the block RAM (even if it's not used).

 

The exception to this rule is UltraRAM on the new UltraScale devices. UltraRAM can only be initialized to zero, presumably in order to keep the UltraRAM blocks relatively small/simple.

Moderator
Posts: 8,401
Registered: ‎02-27-2008

Re: Can't $initial be synthesized?

A comment (I teach a university class, too),

 

Specifying initial values in a FPGA device is only needed if you do not wish '0' as the initial value, which is the default for DFF, LUTRAM, SRL, BRAM, etc.

 

It would be different if you were designing an ASIC.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Scholar
Posts: 722
Registered: ‎03-22-2016

Re: Can't $initial be synthesized?

@cmpt_design

This can be easily tested

Create a simple design (zynq or microblaze) and then go Tools/Create-Package IP/Create new AXI4...

Add just one axi-lite slave interface with say 8 registers. Hit OK then "Edit". 

Double click the verilog file in "sources" and scroll down to the reset block (bunch of "slave_reg0 <= 0;" lines)  comment out all of the assignments.

Then above that create an initial block like 

initial begin

slave_reg0 <= 1;

slave_reg1 <= 2;

...

end

Save and go back to your design. Insert the IP you just created. 

Create the bitfile and launch SDK. Create a hello world application. Then after printing hello world, do a loop 1..16 and print the values of the memory starting at the start position of your AXI lite interface (found in xparameters.h). You should see 1..2..3..4..

 


* Henry Bucher, Baremetal Labs, Extreme Financial Engineering: btlabs.us
Scholar
Posts: 722
Registered: ‎03-22-2016

Re: Can't $initial be synthesized?

@cmpt_design 

I am getting good at this video business. Here is a quick proof that initial blocks are synthesizable. 

https://youtu.be/xyvhy0rUdiE

 

 

 


* Henry Bucher, Baremetal Labs, Extreme Financial Engineering: btlabs.us