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Adventurer
Adventurer
952 Views
Registered: ‎11-08-2017

Clock Gaters Tree -> routing conjection

Hi All,

 

Please see below the tree structures of the Clock Gaters in FPGA.

 

There are a PLL, several Center Gaters (controlled by SW), and many hierarchies with local Clock Gaters, which are controlled by Internal Logic.

 

The problem is so that the lines, which are shown in RED, take a lot of routing resources. The Global Lines could not be taken in account sinse they are used for another purposes.

 

So, what's the solution in order to reduce the routing resources? Keeping two hierarchies for clock gating is MUST(the first hierarchy is for SW Clock Control, the second hierarchy is for Logic Clock Control). 

 


GatersTree.jpg


 

Thank you!

 

GatersTree.jpg
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Moderator
Moderator
851 Views
Registered: ‎01-16-2013

Re: Clock Gaters Tree -> routing conjection

@dmitryl_home

 

Check "Optimizing High Fanout" in below UFDM user guide: 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug949-vivado-design-methodology.pdf#page=248

 

--Syed

 

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Did you check our new quick reference timing closure guide (UG1292)?
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Adventurer
Adventurer
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Registered: ‎11-08-2017

Re: Clock Gaters Tree -> routing conjection

Should I put a Global Clock Buffer on each Gated Clock (in order to keep minimal skew)?

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Moderator
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Registered: ‎01-16-2013

Re: Clock Gaters Tree -> routing conjection

@dmitryl_home

 

Is this an ASIC prototyping project? You can insert Global buffer to reduce the skew however, excessive global utilization may also lead to over clock utilization errors. Check if the discussion in below forum thread helps:

https://forums.xilinx.com/t5/Timing-Analysis/how-to-solve-clock-path-skew-high-hold-violation/td-p/479156

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Adventurer
Adventurer
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Registered: ‎11-08-2017

Re: Clock Gaters Tree -> routing conjection

'Is this an ASIC prototyping project' - yes

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: Clock Gaters Tree -> routing conjection

@dmitryl_home

 

Thanks! Check the forum link in my previous post and see if the discussion on clock gating helps. 

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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