09-08-2018 12:26 PM - edited 09-08-2018 12:26 PM
Please see below the tree structures of the Clock Gaters in FPGA.
There are a PLL, several Center Gaters (controlled by SW), and many hierarchies with local Clock Gaters, which are controlled by Internal Logic.
The problem is so that the lines, which are shown in RED, take a lot of routing resources. The Global Lines could not be taken in account sinse they are used for another purposes.
So, what's the solution in order to reduce the routing resources? Keeping two hierarchies for clock gating is MUST(the first hierarchy is for SW Clock Control, the second hierarchy is for Logic Clock Control).
09-17-2018 05:04 AM
Check "Optimizing High Fanout" in below UFDM user guide:
09-29-2018 11:50 PM
Is this an ASIC prototyping project? You can insert Global buffer to reduce the skew however, excessive global utilization may also lead to over clock utilization errors. Check if the discussion in below forum thread helps:
10-01-2018 12:14 AM
Thanks! Check the forum link in my previous post and see if the discussion on clock gating helps.