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Registered: ‎05-09-2014

Clock Placement Issue with Example Design XAPP1315

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All:

     I'm trying to implement the CameraLink example design in XAPP1315.  My clocks input comes from an FMC card that provides the interface between the FPGA and the CameraLink cable.  Based on the information provided below I've tried using a IBUFGDS_DIFF_OUT and a IBUFDS_DIFF_OUT, both give me the same error messages below.  The example design uses both the positive and negative version of the input clock.

     I also tried to connect the clock outputs from the IBUFGDS_DIFF_OUT/IBUFDS_DIFF_OUT to BUFGs but that gives me a new set of errors that prevent the FPGA to implement successfully.

    My working theory is that this is a clock pin placement issue which I can't change.  In the past I've gotten a suggested workaround using CLOCK_DEDICATED_ROUTE, but this time I didn't.

    Can anyone suggest a solution to this problem or some kind of workaround.

        Thanks,

          Marv

[Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM.
cl_top/rx_channel1/rxc_gen/iob_clk_in/IBUFCTRL_MASTER (IBUFCTRL.O) is locked to IOB_X1Y132
cl_top/rx_channel1/rxc_gen/rx_mmcm_adv_inst (MMCME3_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME3_ADV_X0Y7

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
cl_top/rx_channel1/rxc_gen/bg_px (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y172

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: A MMCM driving a BUFG must be placed in the same clock region of the device as the
BUFG
cl_top/rx_channel1/rxc_gen/rx_mmcm_adv_inst (MMCME3_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME3_ADV_X0Y7
cl_top/rx_channel1/rxc_gen/bg_px (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y172

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
cl_top/rx_channel1/rxc_gen/bg_rxdiv2 (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y171

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
cl_top/rx_channel1/rxc_gen/bg_rxdiv8 (BUFGCE_DIV.O) is provisionally placed by clockplacer on BUFGCE_DIV_X0Y28

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
cl_top/rx_channel1/rxc_gen/iserdes_m (ISERDESE3.CLK) is locked to BITSLICE_RX_TX_X1Y132

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
cl_top/rx_channel1/rxc_gen/iserdes_m (ISERDESE3.CLKDIV) is locked to BITSLICE_RX_TX_X1Y132

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
cl_top/rx_channel1/rxc_gen/iserdes_m (ISERDESE3.CLK_B) is locked to BITSLICE_RX_TX_X1Y132

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
cl_top/rx_channel1/rxc_gen/iserdes_s (ISERDESE3.CLK) is locked to BITSLICE_RX_TX_X1Y133

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
cl_top/rx_channel1/rxc_gen/iserdes_s (ISERDESE3.CLKDIV) is locked to BITSLICE_RX_TX_X1Y133

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
and cl_top/rx_channel1/rxc_gen/iserdes_s (ISERDESE3.CLK_B) is locked to BITSLICE_RX_TX_X1Y133

 

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318 Views
Registered: ‎05-09-2014

Calibra:

      Changing to clock going to my MicroBlaze seems to make the interface work.  I'm now recovering test patterns from the Camera.  Many thanks for helping.

        Marv

 

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704 Views
Registered: ‎01-22-2015

@marvinscheinbart 

Page 50 of UG571(v1.12) says that OB output of IBUFDS_DIFF_OUT has no direct connection to a clock buffer.  So, ensure you are connecting the O-output and not OB-output to the buffer/PLL.

Mark

 

 

 

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Registered: ‎05-09-2014

All:

     Thanks for trying to help.  I'm trying to implement the XAPP1315 example design as is.  The only changes I made is adding the pinout of the FMC card to an xdc file.  One of the things I tried was to add BUFGs to the clock output of the IBUFDS_DIFF_OUT.  This gives me the error messages shown below.

      Any suggestions would greatly appreciated.

        Marv

[Place 30-650] Non IO buffer cl_top/rx_channel1/rxc_gen/BUFG_P_II{BUFGCE} is driving IDATAIN pin of IDELAY instance cl_top/rx_channel1/rxc_gen/idelay_cm. This will lead to unroutable situation. IDATAIN pin of IDELAY instance should always get signal from IO buffer or GND.


[Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.


[Common 17-69] Command failed: Placer could not place all instances

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Voyager
Voyager
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Registered: ‎06-20-2012

Hi,

Input pin of IDATAIN block can only be connected to an input buffer and not to a BUFG clock buffer.

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Registered: ‎05-09-2014

Calibra:

     As I mentioned I'm trying to implement the XAPP1315 example project.  The example project is wire as you pointed out.  During the implementation phase I get the below error messages.  I've tried the BUFG insertion method as suggested by the error message but that gives me all sorts of other error messages.

      Any suggestions would be greatly appreciated.

       Marv

 

 

[Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM.
cl_top/rx_channel1/rxc_gen/iob_clk_in/IBUFCTRL_MASTER (IBUFCTRL.O) is locked to IOB_X1Y132
cl_top/rx_channel1/rxc_gen/rx_mmcm_adv_inst (MMCME3_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME3_ADV_X0Y7

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
cl_top/rx_channel1/rxc_gen/bg_px (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y172

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: A MMCM driving a BUFG must be placed in the same clock region of the device as the
BUFG
cl_top/rx_channel1/rxc_gen/rx_mmcm_adv_inst (MMCME3_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME3_ADV_X0Y7
cl_top/rx_channel1/rxc_gen/bg_px (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y172

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
cl_top/rx_channel1/rxc_gen/bg_rxdiv2 (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y171

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
cl_top/rx_channel1/rxc_gen/bg_rxdiv8 (BUFGCE_DIV.O) is provisionally placed by clockplacer on BUFGCE_DIV_X0Y28

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
cl_top/rx_channel1/rxc_gen/iserdes_m (ISERDESE3.CLK) is locked to BITSLICE_RX_TX_X1Y132

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
cl_top/rx_channel1/rxc_gen/iserdes_m (ISERDESE3.CLKDIV) is locked to BITSLICE_RX_TX_X1Y132

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
cl_top/rx_channel1/rxc_gen/iserdes_m (ISERDESE3.CLK_B) is locked to BITSLICE_RX_TX_X1Y132

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
cl_top/rx_channel1/rxc_gen/iserdes_s (ISERDESE3.CLK) is locked to BITSLICE_RX_TX_X1Y133

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
cl_top/rx_channel1/rxc_gen/iserdes_s (ISERDESE3.CLKDIV) is locked to BITSLICE_RX_TX_X1Y133

Clock Rule: rule_floating_clklds_in_half_column
Status: PASS
Rule Description: Floating ISERDESs/OSERDESs/IDELAYs/ODELAYs (ones without an associated IOB) loads
of global clock buffers like BUFGCE/BUFGCTRL/BUFGCE_DIV must be placed such that there are not more
than 6 clock nets in an IO half bank
and cl_top/rx_channel1/rxc_gen/iserdes_s (ISERDESE3.CLK_B) is locked to BITSLICE_RX_TX_X1Y133

 

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Voyager
Voyager
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Registered: ‎06-20-2012

I have implemented XAPP1315  example design as is without any problems.

Can you share your design.

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Registered: ‎05-09-2014

Calibra:

      I archive my project but it's larger than 19MB which is the limit to attach to a post.  I'm going to try to use EZmove when I get a password issue fixed.  I will let you know.

      Marv

 

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Voyager
Voyager
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Registered: ‎06-20-2012

RTL sources + XDC files + target device is enough to reproduce the problem.

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Registered: ‎05-09-2014

Calibra:

      Something interesting happened.  I wanted to send you a project archive but it was very large.  I decided to strip down the project to just the Cameralink interface logic.  When I remove my MicroBlaze processor core which runs the Camera Link UART interface all my errors went away.  I think it has something to do with the clocks I'm using to run the MicroBlaze.  Before I send you anything I'm going to re-arrange my clocks to see if this will solve my problem.  This has to be the issue.

     Thanks for trying to help.  I'll keep you posted.

        Marv

 

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Highlighted
319 Views
Registered: ‎05-09-2014

Calibra:

      Changing to clock going to my MicroBlaze seems to make the interface work.  I'm now recovering test patterns from the Camera.  Many thanks for helping.

        Marv

 

View solution in original post

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