Clock runs 100 MHz though design says 50 MHz

[Agner]

The implemented design on my A7 board runs 100 MHz though the design says 50 MHz.

The constraints file has:

set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clock]
create_clock -period 20.000 -name sys_clk -waveform {0.000 10.000} -add [get_ports clock]

The top module has:

module top (
    input clock,                 // system clock 50 MHz
...
);
...
// test clock rate. Should count at 1 Hz
reg [28:0] clock_test_divider = 0;
reg [7:0] clock_test = 0;
always_ff @(posedge clock) begin
    if (clock_test_divider == 50000000) begin
        clock_test_divider = 0;
        clock_test = clock_test + 1;
    end else begin
        clock_test_divider = clock_test_divider + 1;
    end
end

The clock_test signal is connected to a display that counts at 2Hz, rather than the expected 1Hz.

"Report Clock Networks" under "Synthesis" says:

sys_clk (50.00 MHz) (drives 986 loads)
  > clock
    > I
      > etc.

The design has no other clocks. If I change the name clock to sys_clk in the .sv files, I get error messages for the constraints.

I am using Vivado 2020.1 with an Artix-7 board.

What is wrong?

[bruce_karaffa]

Have you looked at the input clock with a scope to verify that it is 50MHz?

[joancab · Accepted solution]

The create_clock constraint is for simulation and timing, it will not create any clock when you "run" the design (if by "run" you mean the real thing in real hardware). 

In your code you are toggling the lowest bit of clock_test at a frequency of Fin/50e6, so the frequency should be Fin/50e6/2. 

If you have clock_test(0) connected to a pin and an LED or whatever and see 2 Hz, then Fin = 200 MHz. sorry if I make things weirder.

[dpaul24]

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@Agner ,

Are you using a MMCM/PLL in your design? If so, you should re-check its config settings once again.

If the board input clock is directly used in the design (although this is not a recommended way), then you should physically check the input clock with a scope.

[joancab]

This is what you have, you cannot change that with a constraint:

Source: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual

[Agner]

Thank you for a quick answer. I thought that the create_clock constraint was actually creating a clock. How do I know which constraints are for simulation only?

[joancab]

Constraints just set conditions to simulation and synthesis. In the case of a create_clock, you tell Vivado about the period of a clock (that must be physically match that frequency) in order to check other conditions like timing, delays, etc.

So, all constraints are just "fences" to mark the "good" and the "bad" outcomes. If they were code, why calling them by another name?

You can have any frequency, even many (well, a few) different clock frequencies by using an MMCM block that you can drop into a block diagram from the IP catalog or instantiate in HDL (see the templates pop-up)

[Agner]

What about constraints like this:

set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports switch0]

I thought that this sets the voltage level of an input/output pin and connects it to a signal name in the code. It is listed under constraints, yet it is not just simulation.

And what about this

set_property CONFIG_VOLTAGE 3.3 [current_design]

Is this setting a physical voltage, or just simulation?

[joancab]

There is a Constraints User Guide (UG903) that you can refer to. 

Your first constraint doesn't set any voltage, remember that constraints change nothing, it only sets the pin standard to be LVCMOS3V3. This requires in turn the bank where that pin is to be powered at 3V3.

The second expresses (note I avoid 'set') the configuration interface voltage, that has to match the actual value in the board.

you may think it's redundant. Well, FPGAs have different voltage possibilities for different banks, so that information must be somewhere in the configuration because i/o ports are initialized along with your HDL code written into the FPGA.

A last word of caution: if you don't know what you are doing, don't fiddle with these constraints (about voltages), it may result expensive.

[bruce_karaffa]

The PACKAGE_PIN J15 [get_ports switch0]  connects pin J15 to the port (signal) in your design.  The LVCMOS33 does not set the input or output voltage.  It tells vivado what the IO standard is on that pin.  If the IO bank is powered by 3.3V, the output will indeed go up to nearly 3.3V and down to ground.  If the bank is powered by something other than 3.3V, the output will still do something.  Xilinx won't guarantee exactly what or what the timing might be.  If the pin is an input, the input signal voltage must match the setting and the voltage that is powering the IO bank.