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Registered: ‎11-24-2017

Clock wizard module wont work with mine.

Hello all,

I am trying to implement a clock divider module and a phase shift module together but it keeps failing.

The phase shift module was generated using the core generator clock wizard.

The clock divider module works perfectly fine, and implements, without the phase shift module.


here are the errors that I am getting


ERROR:NgdBuild:455 - logical net 'u1/sclclk' has multiple driver(s):
ERROR:NgdBuild:462 - input pad net 'u1/sclclk' drives multiple buffers:
ERROR:NgdBuild:924 - input pad net 'u1/sclclk' is driving non-buffer primitives:
ERROR:NgdBuild:947 - input pad net 'u1/sclclk' is driving non-input buffer(s):


I am using ISE 14.7 and planning to implement this on a mojo v3 board that has a spartan 6 chip on it


here is my code

wire rst = ~rst_n; // make reset active high
wire phasedclock;

// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[7:2] = 6'b0;

clock u1 (.clk(clk), .clkscale(50000000/2), .sclclk(led[0]));
clock u2 (.clk(clk), .clkscale(50000000/2), .sclclk(phasedclock));

  phaseShiftClock90 u3
   (// Clock in portsS
    .CLK_IN1(phasedclock),      // IN
    // Clock out ports
    .CLK_OUT1(led[1]));    // OUT   


the clock module I have works.  I start getting this error when I instantiate phaseShiftClock90.


module clock(input clk, input [31:0] clkscale, output reg sclclk);
									// CLK crystal clock oscillator 50 MHz
reg [31:0] clkq = 0;			// clock register, initial value of 0
always@(posedge clk)
		clkq=clkq+1;			// increment clock register
			if (clkq>=clkscale)  	// clock scaling
					sclclk=~sclclk;	// output clock
					clkq=0;		// reset clock register




here is the HDL functional model of the phaseShiftClock90

// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
// CLK_OUT1____50.000_____90.000______50.0______300.000____150.000
// "Input Clock   Freq (MHz)    Input Jitter (UI)"
// __primary______________50____________0.010

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "phaseShiftClock90,clk_wiz_v3_6,{component_name=phaseShiftClock90,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module phaseShiftClock90
 (// Clock in ports
  input         CLK_IN1,
  // Clock out ports
  output        CLK_OUT1

  // Input buffering
  IBUFG clkin1_buf
   (.O (clkin1),
    .I (CLK_IN1));

  // Clocking primitive

  // Instantiation of the DCM primitive
  //    * Unused inputs are tied off
  //    * Unused outputs are labeled unused
  wire        psdone_unused;
  wire        locked_int;
  wire [7:0]  status_int;
  wire clkfb;
  wire clk0;
  wire clk90;

  #(.CLKDV_DIVIDE          (2.000),
    .CLKFX_DIVIDE          (1),
    .CLKFX_MULTIPLY        (4),
    .CLKIN_DIVIDE_BY_2     ("FALSE"),
    .CLKIN_PERIOD          (20.0),
    .CLK_FEEDBACK          ("1X"),
    .PHASE_SHIFT           (0),
    .STARTUP_WAIT          ("FALSE"))
    // Input clock
   (.CLKIN                 (clkin1),
    .CLKFB                 (clkfb),
    // Output clocks
    .CLK0                  (clk0),
    .CLK90                 (clk90),
    .CLK180                (),
    .CLK270                (),
    .CLK2X                 (),
    .CLK2X180              (),
    .CLKFX                 (),
    .CLKFX180              (),
    .CLKDV                 (),
    // Ports for dynamic phase shift
    .PSCLK                 (1'b0),
    .PSEN                  (1'b0),
    .PSINCDEC              (1'b0),
    .PSDONE                (),
    // Other control and status signals
    .LOCKED                (locked_int),
    .STATUS                (status_int),
    .RST                   (1'b0),
    // Unused pin- tie low
    .DSSEN                 (1'b0));

  // Output buffering
  BUFG clkf_buf
   (.O (clkfb),
    .I (clk0));

  BUFG clkout1_buf
   (.O   (CLK_OUT1),
    .I   (clk90));

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5 Replies
Registered: ‎01-16-2013

Re: Clock wizard module wont work with mine.



In the clocking Wizard IP, did you select "external feedback". Check the below forum thread:



Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Registered: ‎06-21-2017

Re: Clock wizard module wont work with mine.

The clock divider module is using logic resources to divide the clock.  This is then explicitly routed to a clock buffer before going into the clocking wizard's DCM.  As the error messages show, this breaks a number pf placement rules.  Are the divided and phase shifted clocks really being used as clocks in the FPGA or are they being used as logic signals?

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Registered: ‎11-24-2017

Re: Clock wizard module wont work with mine.

I am trying to mimic the output of several quardature encoders. So these are going to be used as logic signals, hopefully on the i/o.

Is there a better way to do this?


I also tried connecting the clock directly to the phase shift module.  it said that there were illegal connections. 


all I want are two square waves, one that is 90 degrees out of phase with the other.  I need to be able to adjust the frequency of these waves also.  

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Registered: ‎06-21-2017

Re: Clock wizard module wont work with mine.

You already have a counter that rolls over at your desired frequency.  Make one of your encoder phases go high at count=0 and low at count=clkscale/2.  Make the other phase go high at clkscale/4 and low at 3clkscale/4.

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Registered: ‎06-21-2017

Re: Clock wizard module wont work with mine.

I just wanted to mention, in the real world, quadrature encoders can look pretty noisy if you are looking at them at multi MHz speeds.  You might want something that looks like simple filtering/debounce code if you interface to a real encoder.

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