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Registered: ‎07-29-2009

Clocks and JESD204B V7.1

I'm trying to do a custom design.  I have an external clock (VCO) available.  I have a few questions.  We purchased the 7.1 JESD204B license.

We are interfacing with the TI DAC39J82 DAC at the highest rate zynq 7z30 -2 can go : 10.3125 GHz over 4 lanes (421 = LMF).  For the 10.3125 line rate, I have selected a reference clock speed of 206.25 (from the wizard).  I can select any of them I think, but here are my questions:

1) Does my external VCO need to supply the 206.25 MHz frequency on a MRCC pin?  Or can I provide any frequency and use a Fabric/local MCCM/PLL to generate it?  How accurately does this clock need to be to ensure no failure of the 10.3125 GHz transceiver?

2) Should the DRP/AXI clock also be externally generated and supplied to a MRCC pin?  Are there combinations of MRCC pins that are best to use with the JESD204B ipcore?

3) Where can I find out more information about JESD204B clocking like this for the zynq?


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