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Observer mnanoop2014
Observer
287 Views
Registered: ‎10-29-2018

Clocks in XDC

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I am new to Vivado.

 

I have a simple design wherein I've to initialize a 4MHz clock (main_clk) as one of the inputs to the top module.
Presently, I am using these lines in my xdc file:

set_property -dict {IOSTANDARD LVCMOS33} [get_ports main_clk]
create_clock -add -name main_clk -period 250.00 [get_ports {main_clk}];

An error pops up during bitstream generation:

[DRC UCIO-1] Unconstrained Logical Port: 1 out of 6 logical ports have no 
user assigned specific location constraint (LOC). This may cause I/O contention
or incompatibility with the board power or connectivity affecting performance,
signal integrity or in extreme cases cause damage to the device or the
components to which it is connected. To correct this violation, specify all
pin locations. This design will fail to generate a bitstream unless all logical
ports have a user specified site LOC constraint defined. To allow bitstream
creation with unspecified pin locations (not recommended), use this command:
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the
Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to
a .tcl file and add that file as a pre-hook for write_bitstream step for the
implementation run. Problem ports: main_clk.

If I don't specify the IOSTANDARD, even then an error pops up asking me to declare the IOSTANDARD.

I do not intend to use any external clock supply. I understand there is a clock generator from which we can derive smaller frequency clocks. Any references I can use to resolve this issue?

Also, if I have to use a pin for this, can I use any output pins on the board, specifically an LED (Does it damage it in anyway)?

I am using Zynq Ultrascale+ MPSoC ZCU102 Evaluation board with 2017.4 version Vivado in Ubuntu 16.04

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Historian
Historian
237 Views
Registered: ‎01-23-2009

Re: Clocks in XDC

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Your confusion (probably) comes from the name of the constraint "create_clock". The "create_clock" command does not "create" a "clock", it merely describes a clock that must already exist in the system.

All constraints are there to provide mechanisms of describing the timing of the system external to the FPGA so that the tools can understand how the FPGA has to perform. So a create_clock command is applied to a port of the design that has a PACKAGE_PIN location of a pin of the FPGA that is connected to an external oscillator (and describe the characteristics of that external oscillator).

There are no "internally generated clocks" in the FPGA (except for the "Configuration Clock" which is not very precise and is very hard to use for general purpose clocking) - the FPGAs have "Clock Management Tiles" which contain MMCMs and PLLs (or in older technologies DCMs) which can modify a clock - generate a clock of a new frequency from an existing clock, but all of these need an input clock to operate, and this input clock must come from a real source - i.e. an oscillator outside the FPGA.

The ZCU102 has a number of clocks provided to the FPGA - if you look at UG1182 - the ZCU102 Evaluation Board User Guide - there is a section on "Clock Generation" where it describes 13 different clock sources on the FPGA. Several are for dedicated usage (like HDMI or the GTR or other MGTs), but several are available for "general purpose" use. If you are using the Programmable System (PS), then it provides the PSCLK to the programmable logic; the PSCLK's frequency is set by registers in the PS using the PS_REF_CLK (of 33.33MHz). If you don't want to use that clock you have a differential input 74.25MHz (CLK_74_25) and 125MHz (CLK125) oscillator on specific pins (AK15/AK14 and G21/F21), as well as a programmable clock (USER_SI570) which is set to 300MHz by default on pins AL8/AL7).

Whichever one you use, you tell the tool you are using it using constraints - so for example for CLK_125:

set_property IO_STANDARD LVDS_25 [get_ports {clk_125_p clk_125_n}
set_property PACKAGE_PIN G21 [get_ports clk_125_p]
set_property PACKAGE_PIN F21 [get_ports clk_125_n]
create_clock -name user_clk -period 8 [get_ports clk_125_p]

This tells the clock what pins you are planning to use for the port clk_125_p/n (which would be port definitions at the top of your design) and that it can expect a 125MHz LVDS_25 clock input on that pin.

You can use any of these clocks either directly (via a BUFG) or using an MMCM to generate a clock of a different frequency (also via a BUFG). I will warn you, though, that 4MHz is VERY slow for an FPGA - the MMCM can only go down 6.25MHz. For slower clocks you need to consider some kind of clock gating or enabling.

Avrum

4 Replies
Explorer
Explorer
244 Views
Registered: ‎05-21-2015

Re: Clocks in XDC

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@mnanoop2014,

You need to assign locations to all ports.  If you do not, some of the unsigned ports may be assigned to the same bank as main_clk but with an incompatible I/O standards.  You will then get a confusing DRC error such as this one.

Dan

Highlighted
Historian
Historian
238 Views
Registered: ‎01-23-2009

Re: Clocks in XDC

Jump to solution

Your confusion (probably) comes from the name of the constraint "create_clock". The "create_clock" command does not "create" a "clock", it merely describes a clock that must already exist in the system.

All constraints are there to provide mechanisms of describing the timing of the system external to the FPGA so that the tools can understand how the FPGA has to perform. So a create_clock command is applied to a port of the design that has a PACKAGE_PIN location of a pin of the FPGA that is connected to an external oscillator (and describe the characteristics of that external oscillator).

There are no "internally generated clocks" in the FPGA (except for the "Configuration Clock" which is not very precise and is very hard to use for general purpose clocking) - the FPGAs have "Clock Management Tiles" which contain MMCMs and PLLs (or in older technologies DCMs) which can modify a clock - generate a clock of a new frequency from an existing clock, but all of these need an input clock to operate, and this input clock must come from a real source - i.e. an oscillator outside the FPGA.

The ZCU102 has a number of clocks provided to the FPGA - if you look at UG1182 - the ZCU102 Evaluation Board User Guide - there is a section on "Clock Generation" where it describes 13 different clock sources on the FPGA. Several are for dedicated usage (like HDMI or the GTR or other MGTs), but several are available for "general purpose" use. If you are using the Programmable System (PS), then it provides the PSCLK to the programmable logic; the PSCLK's frequency is set by registers in the PS using the PS_REF_CLK (of 33.33MHz). If you don't want to use that clock you have a differential input 74.25MHz (CLK_74_25) and 125MHz (CLK125) oscillator on specific pins (AK15/AK14 and G21/F21), as well as a programmable clock (USER_SI570) which is set to 300MHz by default on pins AL8/AL7).

Whichever one you use, you tell the tool you are using it using constraints - so for example for CLK_125:

set_property IO_STANDARD LVDS_25 [get_ports {clk_125_p clk_125_n}
set_property PACKAGE_PIN G21 [get_ports clk_125_p]
set_property PACKAGE_PIN F21 [get_ports clk_125_n]
create_clock -name user_clk -period 8 [get_ports clk_125_p]

This tells the clock what pins you are planning to use for the port clk_125_p/n (which would be port definitions at the top of your design) and that it can expect a 125MHz LVDS_25 clock input on that pin.

You can use any of these clocks either directly (via a BUFG) or using an MMCM to generate a clock of a different frequency (also via a BUFG). I will warn you, though, that 4MHz is VERY slow for an FPGA - the MMCM can only go down 6.25MHz. For slower clocks you need to consider some kind of clock gating or enabling.

Avrum

Observer mnanoop2014
Observer
194 Views
Registered: ‎10-29-2018

Re: Clocks in XDC

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Hi Avrum,

Thanks a lot for your response. I have a few more questions regarding the same. If there is any reference material or an example design for this, it'd be very helpful. 

Specifically, I tried the below set of lines in my xdc:

set_property IOSTANDARD DIFF_SSTL12 [get_ports {USER_SI570_P USER_SI570_N]
set_property PACKAGE_PIN AL8 [get_ports USER_SI570_P]
set_property PACKAGE_PIN AL7 [get_ports USER_SI570_N]
create_clock -name main_clk -period 250.00 [get_ports USER_SI570_P]
set_property IOSTANDARD LVCMOS33 [get_ports {main_clk}]
set_property PACKAGE_PIN AL12 [get_ports {main_clk}]

The last two lines are because the bitstream generation specifically threw an error saying IOSTANDARD and PACKAGE_PIN weren't declared for main_clk (Do I need to do this?).

Also, in my top module, I have just the main_clk declared as input. I haven't declared PS_REF_CLK as input (Must I?). 

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Observer mnanoop2014
Observer
145 Views
Registered: ‎10-29-2018

Re: Clocks in XDC

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 I was wrong in my understanding of how clocks worked. 

What works now:
I derive the clock signal from one of the 13 or so sources mentioned and I use a clocking wizard IP to manipulate it's the frequency to whatever value I want. So the period I mentioned in the XDC has to correspond to the period the actual clock is said to be of. Not one I want it to be. Later, in the IPI, I can derive frequencies I want from it. Also, the top module has to have the inputs of main clocks I use. 

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