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Visitor baldwin
Visitor
1,392 Views
Registered: ‎01-21-2018

Combining 3 3-bit ports into 1 8-bit port

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 For my assignment, I have to connect a counter to the register file. Obviously, this is not the full code, I've only included the components:

 

Counter:

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;



Entity Counter is
      Generic ( Delay:   Time := 8 ns );
      Port (    Clk : In    std_logic;
                Inc : In    std_logic;
                Rst : In    std_logic;
                i : Out   std_logic_vector(2 downto 0);
                j : Out   std_logic_vector(2 downto 0);
                k : Out   std_logic_vector(2 downto 0) );
End Counter;

Architecture BEHAVIORAL of Counter is

   Begin
    P: Process ( Clk )
    Variable Value : UNSIGNED( 8 downto 0 ) := "000000000";
    Begin
        if( Clk'event and Clk = '1' ) then 
            if( Rst = '1' ) then
                Value := "000000000";
            elsif( Inc = '1' ) then
                Value := Value + 1;
            End if;
        End if;
                i(2) <= Value(8) after Delay;
                i(1) <= Value(7) after Delay;
                i(0) <= Value(6) after Delay;
                j(2) <= Value(5) after Delay; 
                j(1) <= Value(4) after Delay;
                j(0) <= Value(3) after Delay;
                k(2) <= Value(2) after Delay;
                k(1) <= Value(1) after Delay; 
                k(0) <= Value(0) after Delay;                    
    End Process P;

End BEHAVIORAL;

 

Reg:

Library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
Entity RegFile IS
   Generic ( Delay:   Time := 8 ns );
   Port (R_addr1,R_addr2,W_addr: IN std_logic_vector(7 DOWNTO 0);
         R_en1,R_en2, W_en: IN std_logic;
         R_data1, R_data2: OUT INTEGER; 
         W_data: IN INTEGER; 
         Clk: IN std_logic );
End RegFile;

Architecture Behavioral OF RegFile IS 
    type RF is array ( 0 to 31, 0 to 7 ) of INTEGER;
    signal Storage : RF := (
             ...); --8 x 8 matrices
Begin
    WriteProcess: Process(Clk)
    Variable col_w:std_logic_vector(2 DOWNTO 0);    
    Variable row_w:std_logic_vector(4 DOWNTO 0);
    Begin
          row_w := W_addr(7 downto 3);
          col_w := W_addr(2 downto 0);
        
    if( Clk'event and Clk = '1' ) then   
      if(W_en = '1') then 
        -- write --
        Storage( CONV_INTEGER(row_w), CONV_INTEGER(col_w)) <= W_data after Delay;
      End if;
        
    End if;
    
    End Process;

    ReadProcess: Process(R_en1, R_addr1, R_en2, R_addr2,Storage)
    Variable  col_r1, col_r2:std_logic_vector(2 DOWNTO 0);  
    Variable  row_r1, row_r2:std_logic_vector(4 DOWNTO 0);
    Begin
        row_r1 := R_addr1(7 downto 3);
        col_r1 := R_addr1(2 downto 0);
        row_r2 := R_addr2(7 downto 3);
        col_r2 := R_addr2(2 downto 0);
    
    if(R_en1 = '1') then 
        R_data1 <= Storage( CONV_INTEGER(row_r1), CONV_INTEGER(col_r1) ) after Delay;
    else
        R_data1 <= INTEGER'left;    
    End if;
    
    if(R_en2 = '1') then 
        R_data2 <= Storage( CONV_INTEGER(row_r2), CONV_INTEGER(col_r2) ) after Delay;
    else
        R_data2 <= INTEGER'left;    
    End if;
    End Process;
End Behavioral;

 

I am attempting to use the counter to drive my address signals (write address, read address). Problem is, counter only outputs i, j, and k, each 3 bits, whereas the addresses take 8 bit inputs.

 

I am not allowed to change the codes of the components, so I am wondering if there is a way to combine i, j, and k to the address in the port mapping.

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1 Solution

Accepted Solutions
Scholar u4223374
Scholar
2,008 Views
Registered: ‎04-26-2015

Re: Combining 3 3-bit ports into 1 8-bit port

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You can certainly combine signals, the term you need is "concatenation" and there's a thread about it here.

 

However, you obviously can't put 9-bit data into an 8-bit port without losing some data. You will need to determine the appropriate way to deal with this.

4 Replies
Scholar u4223374
Scholar
2,009 Views
Registered: ‎04-26-2015

Re: Combining 3 3-bit ports into 1 8-bit port

Jump to solution

You can certainly combine signals, the term you need is "concatenation" and there's a thread about it here.

 

However, you obviously can't put 9-bit data into an 8-bit port without losing some data. You will need to determine the appropriate way to deal with this.

Scholar hbucher
Scholar
1,371 Views
Registered: ‎03-22-2016

Re: Combining 3 3-bit ports into 1 8-bit port

Jump to solution

@baldwin Giving you kudos for being straight about your assignment

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.
0 Kudos
Visitor baldwin
Visitor
1,333 Views
Registered: ‎01-21-2018

Re: Combining 3 3-bit ports into 1 8-bit port

Jump to solution

Thanks, this helps. And yes, I understand that I will be losing some data, as I'm using 9-bit data for an 8-bit input. This question is then followed up, how would I be able to select what part of the data I'm losing? 

 

For example, say I only want to lose the left most bit of the i signal. Would it be correct to do:

 

W_Address <= I(1) & I(0) & J & K;

Also, when I do concatenation like this, I can assume the signals are assigned from left to right? Say I is 010, J is 111, and K is 001, would these be assigned to W_addr in order as 10111001?  

0 Kudos
Scholar u4223374
Scholar
1,300 Views
Registered: ‎04-26-2015

Re: Combining 3 3-bit ports into 1 8-bit port

Jump to solution

@baldwinYes to both questions, although for larger vectors it might be neater to write:

 

W_Address <= I(1 downto 0) & J & K;

This means that for, say, a 32-bit address, you're not writing "I(31) & I(30) & I(29) & I(28) & I(27)..."

 

For the second question, this depends on how you defined the values. In this case:

 

Variable Value : UNSIGNED( 8 downto 0 ) := "000000000";

You've requested a little-endian number, which will mean that bit #0 is on the left and bit #8 is on the right (ie the bits are 876543210).

 

However, if you had defined it like this...

Variable Value : UNSIGNED( 0 to 8 ) := "000000000";

... then that's requesting a big-endian value and the order gets reversed.

 

It'll be much, much easier to just stick with little-endian all the way, in which case your current assumption is exactly correct.

0 Kudos