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Visitor jezgb
Visitor
989 Views
Registered: ‎11-15-2017

Compile stuck in opt_design, Logic Optimization Task

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Hi,

 

I recently upgraded from Vivado 2015.4 to 2018.1, and after updating some IP blocks Vivado synthesized my design.

 

Unfortunately the compile then got stuck in the opt_design phase on the implementation stage, the last log message being "Starting Logic Optimization Task".  Vivado is doing something - it's consuming processor resource and the amount of memory being used varies slowly...

 

I found this thread: https://forums.xilinx.com/t5/Implementation/opt-design-taking-forever/td-p/439800, and having tried the things suggested in it am no closer to a solution.

 

Running implementation with logic optimization disabled works fine, but then fails further down the line, (in routing if memory serves).

 

If I synthesize the design using the GUI and then from the Tcl console run:

 

reset_timing

opt_design

 

the logic optimization task runs just fine.

 

I hope someone can help - I've wasted three days trying to sort this out - I'm going to have to abandon 2018.1 and to switch back to 2015.4 before long...

 

 

Many thanks and best regards,

 

       Jez.

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1 Solution

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Moderator
Moderator
1,285 Views
Registered: ‎02-07-2008

Re: Compile stuck in opt_design, Logic Optimization Task

Jump to solution

Thanks @jezgb. This is the problematic warning:

 

WARNING: [Vivado 12-4379] -period contains time inf which cannot be represented in single precision floating point without rounding by more than 1 picosecond

 

The XDC file, system_util_ds_buf_0_1.xdc, has a period of infinity (inf) instead of an integer.

 

In the Configuration JESD PHY IP settings, ensure the Tx and Rx Line Rates are completed up to at least one decimal place (e.g. 5.0 instead of 5).

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4 Replies
Moderator
Moderator
980 Views
Registered: ‎02-07-2008

Re: Compile stuck in opt_design, Logic Optimization Task

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Hi @jezgb, are there any warnings generated during Processing XDC Constraints in synthesis? Can you upload the synthesis log file?

 

Does the design contain a JESD IP?

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Visitor jezgb
Visitor
974 Views
Registered: ‎11-15-2017

Re: Compile stuck in opt_design, Logic Optimization Task

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Hi @peadard,

 

Thanks for the super-quick reply!

 

My design does use the JESD IP block, and the only warnings in the processing XDC constraints relate to that block:

 

Parsing XDC File [c:/Users/jezgb/Documents/FPGA/cPSD/CrashTestDummy_1/CrashTestDummy_1.srcs/sources_1/bd/system/ip/system_jesd204_0_0/synth/system_jesd204_0_0.xdc] for cell 'PS/system_i/jesd204_0/inst'
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [c:/Users/jezgb/Documents/FPGA/cPSD/CrashTestDummy_1/CrashTestDummy_1.srcs/sources_1/bd/system/ip/system_jesd204_0_0/synth/system_jesd204_0_0.xdc:78]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [c:/Users/jezgb/Documents/FPGA/cPSD/CrashTestDummy_1/CrashTestDummy_1.srcs/sources_1/bd/system/ip/system_jesd204_0_0/synth/system_jesd204_0_0.xdc:80]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [c:/Users/jezgb/Documents/FPGA/cPSD/CrashTestDummy_1/CrashTestDummy_1.srcs/sources_1/bd/system/ip/system_jesd204_0_0/synth/system_jesd204_0_0.xdc:82]
Finished Parsing XDC File [c:/Users/jezgb/Documents/FPGA/cPSD/CrashTestDummy_1/CrashTestDummy_1.srcs/sources_1/bd/system/ip/system_jesd204_0_0/synth/system_jesd204_0_0.xdc] for cell 'PS/system_i/jesd204_0/inst'

Oh, and one other:

 

Parsing XDC File [c:/Users/jezgb/Documents/FPGA/cPSD/CrashTestDummy_1/CrashTestDummy_1.srcs/sources_1/bd/system/ip/system_util_ds_buf_0_1/system_util_ds_buf_0_1.xdc] for cell 'PS/system_i/util_ds_buf_0/U0'
WARNING: [Vivado 12-4379] -period contains time inf which cannot be represented in single precision floating point without rounding by more than 1 picosecond [c:/Users/jezgb/Documents/FPGA/cPSD/CrashTestDummy_1/CrashTestDummy_1.srcs/sources_1/bd/system/ip/system_util_ds_buf_0_1/system_util_ds_buf_0_1.xdc:4]

 

I can post the synthesis log file,  but it's quite long (almost 7500 lines)...

 

 

Many thanks and best regards,

 

        Jez.

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Moderator
Moderator
1,286 Views
Registered: ‎02-07-2008

Re: Compile stuck in opt_design, Logic Optimization Task

Jump to solution

Thanks @jezgb. This is the problematic warning:

 

WARNING: [Vivado 12-4379] -period contains time inf which cannot be represented in single precision floating point without rounding by more than 1 picosecond

 

The XDC file, system_util_ds_buf_0_1.xdc, has a period of infinity (inf) instead of an integer.

 

In the Configuration JESD PHY IP settings, ensure the Tx and Rx Line Rates are completed up to at least one decimal place (e.g. 5.0 instead of 5).

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
jesd.JPG
Visitor jezgb
Visitor
947 Views
Registered: ‎11-15-2017

Re: Compile stuck in opt_design, Logic Optimization Task

Jump to solution

Hi @peadard,

 

Well, I think it's safe to say that I wouldn't have found that solution in a month of Sundays...

 

Many thanks - it whizzed through the logic optimization phase and is now routing.

 

You are a superstar!

 

 

Many thanks and best regards,

 

        Jez.