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Observer sapan533
Observer
8,401 Views
Registered: ‎06-10-2015

Computed clock freq is outside operating range

HI,

In one of my deisgn I am getting the below error during PnR step:

 

ERROR: [DRC 23-20] Rule violation (PDRC-34) MMCM_adv_ClkFrequency_div_no_dclk - The computed value 2800.000 MHz (CLKIN1_PERIOD, net SO) for the VCO operating frequency of the MMCME2_ADV site MMCM\

E2_ADV_X0Y1 (cell wrapper/FLX_PLLAPM_CLK/FLX_PLLAPM_VIRTEX7_inst/i_pll_user_clk) falls outside the operating range of the MMCM VCO frequency for this device (600 - 1600 MHz). The computed value i\

s (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (20.000000), multiplication factor CLKFBOUT_MULT_F (56.000000) or the division fa\

ctor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

 

My XDC file is :

create_clock -add -name {CLK}  -period 100  [get_ports {MB1_CLK_0_p}]
 
create_clock -add -name {FLX_REFERENCE_CLOCK}  -period 5.0  [get_ports {MB1_CLK_0_p}]
 
#
# Generated Clocks
#
 
create_generated_clock -add -name {FLX_PLLAPM_CLK_CLK} -multiply_by 1 -master_clock {CLK}  -source [get_ports {MB1_CLK_0_p}] [get_pins {wrapper/FLX_PLLAPM_CLK/FLX_PLLAPM_VIRTEX7_inst/i_pll_user_c\
lk/CLKOUT0}]
 
create_generated_clock -add -name {FLX_PLLAPM_CLK_IF_CLK} -multiply_by 7 -master_clock {CLK}  -source [get_ports {MB1_CLK_0_p}] [get_pins {wrapper/FLX_PLLAPM_CLK/FLX_PLLAPM_VIRTEX7_inst/i_pll_use\
r_clk/CLKOUT1}]
 
create_generated_clock -add -name {FLX_PLLAPM_CLK_IF_SERIAL_CLK} -multiply_by 14 -master_clock {CLK}  -source [get_ports {MB1_CLK_0_p}] [get_pins {wrapper/FLX_PLLAPM_CLK/FLX_PLLAPM_VIRTEX7_inst/i\
_pll_user_clk/CLKOUT2}]
 
 
I am unable to understand what changes I should make in order to get it working. 
 
 
Can you please suggest what to do ?
 
Rgds
Sapan
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3 Replies
Historian
Historian
8,390 Views
Registered: ‎01-23-2009

Re: Computed clock freq is outside operating range

The problem is that the when the MMCM was generated or instantiated, the parameters given to the MMCM are inconsistent with the system/constraints.

 

I don't know how you generated the MMCM - whether it is hand instantiated or generated through the clocking wizard, but the parameters for the VCO are set in such a way that the VCO would be running too fast.

 

The VCO runs at the input clock frequency multiplied by CLKFBOUT_MULT_F (which is set to 56) divided by DIVCLK_DIVIDE (which is set to 1). The tools seem to think the CLKIN period is 50MHz (20ns), which results in the 2800MHz.

 

Generally when you use an MMCM you have to carefully choose the multipliers based on your input frequency, the desired output frequencies and the legal operating ranges of certain parameters in the MMCM. The best way to do this is to use the clocking wizard from the IP catalog. Even if you choose to manually instantiate the MMCM in the end, its best to start with the clocking wizard so that it can choose the optimum multiplier values. CLKFBOUT_MULT_F=56 is (I think) the maximum value, which is quite unusual - this would only be used for a VERY slow input clock (maximum of 28.5MHz with a DIVCLK_DIVIDE of 1).

 

I don't know where it got the 20ns input clock - it doesn't appear to be from your XDC - clearly thats too fast for this MMCM configuration.

 

So, what is your input clock? How did the MMCM get generated?

 

Most probably, you need to regenerate the MMCM (or change the parameters used during instantiation).

 

Also, one does not need to use create_generated_clock commands on the output of the MMCM. As you can see, the tools understand all the clock multiplication and division done by the MMCM. When a primary clock propagates to an MMCM, the output clocks are all automatically generated by the tools (as generated clocks).

 

Avrum

Observer sapan533
Observer
8,379 Views
Registered: ‎06-10-2015

Re: Computed clock freq is outside operating range

@Avrum

 

Hi,

 

In my synthesiszed netlist , I see the following instantiattion for MMCM :

 

MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(56.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(100.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(56.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(8),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(4),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),

.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))

 

 

DO you see anything worng here? I got this netlist with MMCM instantiation from third party. Need to understand which parameter here should be changed in order to get it working.

 

 

Rgds

Sapan

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Historian
Historian
8,360 Views
Registered: ‎01-23-2009

Re: Computed clock freq is outside operating range

I already answered your question. The parameters for the MMCM are incorrect for your needs. Since I have no idea what your needs are, there is no way I can tell you which parameters to change for what.

 

You have to set the parameters of the MMCM properly for the input and output clocks you are using. The best way to do this is through the clocking wizard - it will help you choose the correct parameters.

 

Avrum

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