Constraining Location shape of design

[charleslili]

Hello,

I have a design that I would like to constrain a sub module to a certain geometry on my FPGA, but I am not really sure how. I am familiar with vivado, but never had to constrain locations before. Basically, I know that a timing intensive section of my design would better meet the timing requirements if it was in a big long rectangle, but instead it is creating a blob. Is there a way to constrain the design such that it builds it within a certain relative location e.g, (within slice X(N) Y(M), X(N +n) Y(M + m))?

I looked around google, but could only find how to set single flip flops and such. Not even sure if this is possible.

Thanks,

Charles

[richardhead]

What makes you think a "big long rectanlge" is the best solution? Most logic I have ever seens is a "blob"

In the first instance, you should look at the timing - and the easiest place to fix it is your code and constraints. Before you go near constraining any areas you should:

1. Ensure all CDCs are constrained correctly (ideally with ASYNC_REG attributes and MAX_DELAYS)

2. Any Multi-cycle paths are constrained

3. Do you have any long logic chains in your design? You should be able to change these in your HDL

Only when the above are exhausted, should you think about area constraints. And they are not any fun, and usually more trouble than they're worth. In most instances where timing fails, its not usually the "blob" of failed logic thats the problem, its another path. The router worked so hard trying to meet that one path it gave up on the others. More often than not its a failed CDC constraint. Any unconstrained path with get a 1ns requirement, and thats usually impossible.

So, I suggest reviewing the design first.

[charleslili]

My design is based on this paper https://www.ncbi.nlm.nih.gov/pmc/articles/PMC5424742/, which states that a rectangular shape for the carry chain works the best.

I have found pblocks, and am trying to use them to get what cells I want where, however, I am hitting an issue of cells being implemented outside of the defined pblock range

[charleslili]

For referance, I have defined my pblock as the highlighted space, but the highlighted cells which should be in it are outside of it.

[richardhead]

The compiler will automatically use the carry chain where necessary. That paper shows the constrained area to be a rectangle not so that the logic will take that shape, but it constrains the logic within that region - it is still likely to be a "blob" within the rectagle.

Usualy pblocks are only needed if you cannot meet timing by other means (HDL, constraints). The issue with them is that they wont be portable between two different boards or projects because the pinouts will be different.

What are you actually trying to do? pblocks should be a final solution, not the first.

[charleslili]

Well, what I am actually trying to do is just implement that paper, with good linearity.

Maybe pblocks aren't the solution, but I do know that for good linearity my array of counters need to have a consistent delay distance between themselves and their respective tapped delay line location. It isn't just about meeting timing,but having consistent delays where they would effect my time reading (which is on the order of picoseconds), as the paper lines out.

And isn't a blob within a rectangle more rectangular?

[richardhead · Accepted solution]

If you need that kind of resolution, then you're probably going to have to do some hand placement, and not for a beginner. It is also not something the majority of people do.

[charleslili]

haha, yeah that's basically what I am doing now. If it needs to happen, that's whats happening.