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Visitor djoconnor
Visitor
559 Views
Registered: ‎12-14-2008

Constraining an entire port

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Hi,

I have 4 16 bit FIFOs that buffer data from an external source and want to apply a constraint to all of them (using set_input_delay).

The hierarchy is USSIO02_inner/LHS1_FIFO, and the port I want to constrain is din.

What is the idiomatic way to do this?

 

I tried..

set_input_delay -clock WCLK -min 12 [get_pins -filter {name =~ "*/din"} -of [get_cells USSIO02_inner/LHS1_FIFO]]

But that complains..

ERROR: [Coretcl 2-67] Invalid object type for 'of_objects'. Supported types: 'sites, bels, iobanks, pkgpin_bytegroups, pkgpin_nibbles, or ports'.

 

Thanks.

 

 

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Xilinx Employee
Xilinx Employee
449 Views
Registered: ‎05-08-2012

Re: Constraining an entire port

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Hi @djoconnor 

These appear to be hierarchical pins based on the name. To constrain pins from a hierarchical module, you can use "get_pins -of [get_cells USSIO02_inner/LHS1_FIFO]".

I would be careful not to constrain pins that you do not intend to. A good option is to specify the pin name with a wildcard. The below specifies only pins starting with "data_".

"get_pins -filter {REF_PIN_NAME=~data_*} -of [get_cells USSIO02_inner/LHS1_FIFO]"

 

To get a range is a little more difficult. The below should give you pins 0-15.

"get_pins -regexp {USSIO02_inner/LHS1_FIFO/din\[([0-9]|1[0-6])\]}"

 


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Moderator
Moderator
543 Views
Registered: ‎01-16-2013

Re: Constraining an entire port

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@djoconnor 

 

Check out example of set_input_delay in below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug903-vivado-using-constraints.pdf#page=102

 

--Syed

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Visitor djoconnor
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Registered: ‎12-14-2008

Re: Constraining an entire port

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Thanks Syed, but I tried something based on example 6, but I get...

set_input_delay -clock WCLK -max 12 [get_pins USSIO02_inner/LHS1_FIFO/din[*]]
CRITICAL WARNING: [Constraints 18-602] set_input_delay: list contains '16' objects of types '(pin)' other than the types '(input port,internal pin)' supported by the constraint. These objects will not be used for this constraint. Please review the object list and ensure unsupported object types are removed.
ERROR: [Constraints 18-472] set_input_delay: list does not contain any object of type(s) '(input port,internal pin)' supported by the constraint. The constraint will not be applied. Please check to make sure that this is intended.

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Moderator
Moderator
513 Views
Registered: ‎11-04-2010

Re: Constraining an entire port

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Hi, @djoconnor ,

For "[get_pins USSIO02_inner/LHS1_FIFO/din[*]]" , please replace it with input ports (ex: get_ports input_port_name)

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Visitor djoconnor
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Registered: ‎12-14-2008

Re: Constraining an entire port

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Hi,

Thanks for your reply but I am not sure what you mean.

If I do "get_ports USSIO02_inner/LHS1_FIFO/din" (or "... din[*]) I get ..

WARNING: [Vivado 12-584] No ports matched 'USSIO02_inner/LHS1_FIFO/din'.

 

I want to trace back from the FIFO port to the external pin but maybe that is not possible.

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Visitor djoconnor
Visitor
471 Views
Registered: ‎12-14-2008

Re: Constraining an entire port

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Alternatively I would like do be able to select a range of a port for constraints, eg IO35[15:0] but I can't work out how to do that either.

 

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Xilinx Employee
Xilinx Employee
450 Views
Registered: ‎05-08-2012

Re: Constraining an entire port

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Hi @djoconnor 

These appear to be hierarchical pins based on the name. To constrain pins from a hierarchical module, you can use "get_pins -of [get_cells USSIO02_inner/LHS1_FIFO]".

I would be careful not to constrain pins that you do not intend to. A good option is to specify the pin name with a wildcard. The below specifies only pins starting with "data_".

"get_pins -filter {REF_PIN_NAME=~data_*} -of [get_cells USSIO02_inner/LHS1_FIFO]"

 

To get a range is a little more difficult. The below should give you pins 0-15.

"get_pins -regexp {USSIO02_inner/LHS1_FIFO/din\[([0-9]|1[0-6])\]}"

 


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

 

 

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------

View solution in original post

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Visitor djoconnor
Visitor
424 Views
Registered: ‎12-14-2008

Re: Constraining an entire port

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OK thanks.

I am pretty surprised/disappointed that what seems like such a basic concept is not trivially done in xdc.

 

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