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herand
Participant
Participant
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Registered: ‎07-24-2017

Constraint Switchbox with PROHIBIT?

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Hello,

 

is there any possibility to prohibit routing through a specific switchbox?

 

I'd like to keep the crosstalk on some route_fixed nets in a switchbox to a minimum and therefore I would like to use the constraint PROHIBIT on it. Is this the correct way? How can I select a switchbox for the set_property command?

 

Or is it not possible to constraint parts of the interconnect in a Xilinx FPGA?

 

Thanks in advance and kind regards,

herand

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austin
Scholar
Scholar
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Registered: ‎02-27-2008

Yes,

 

You may assign specific routes.  Through loc constrains you fix the basic element (DFF, LUT) esily, then using TCL commands you can fix the wires (much much harder).

 

Painful, fraught with difficulties.  Not a supported flow.  Between the TCL guide, and viewing your design in Vivado implemented schematic view, and some experimentation, I am sure you will figure it out.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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austin
Scholar
Scholar
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Registered: ‎02-27-2008

Note that all interconnect is designed for near 0 cross-talk,

 

So you are probably seeing ground bounce due to switching (system jitter) which is a different problem.  System Jitter may be minimized by placing the critical clock edge at -90 degrees from the noisy clock edge (where most core and IO switching occurs.

 

The -90 (+270 degree) is a null, where the influence of the switching (bounce) is at a minimum.

 

It may be just physical distance is helping you now, fooling you into thinking it is cross talk between paths.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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herand
Participant
Participant
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Registered: ‎07-24-2017

Hello austin,

 

thank you for your answer, it's already good to know that crosstalk in interconnects are designed to have no crosstalk and I also read somewhere that they are buffered, which helped me in my design some time.

 

But currently, I'm not trying to reduce crosstalk between different clocks or logic but to isolate ring-oscillators from any other active lines in order to eliminate any possible influence on their oscillation frequency. Therefore I'd like to prohibit the auto-router from routing any wires throught the switchboxes CENTER_INTER_L adjacent to the utilized CLB as I use them to bounce back the signals.

Also, I'd like to know about constraining routing ressources out of curiosity, like the prohibit part.

 

If I may add another question: Is there any deep-knowledge documentation on direct routing, e.g. for Artix-7 devices? By now and as an example: I just have a net I want to route from one LUT in a Slice of a CLB to a LUT in the other Slice of the same CLB. When I use manual routing, I end with a route like this:

"{ CLBLL_L_C CLBLL_LOGIC_OUTS10 NL1BEG1 FAN_ALT4 FAN_BOUNCE4 FAN_ALT0 FAN_BOUNCE0 IMUX_L14 CLBLL_L_B1 }"

 

However, I found it by trial and error and I wondered if there is documentation from which I could learn some of the patterns involved such that I could plan for optimal routes beforehand?

Sorry for the long text, appreciate any answers.

 

Kind regards,

herand

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austin
Scholar
Scholar
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Registered: ‎02-27-2008

h,

 

Good luck with that.  Isolation of ring oscillators will be extremely difficult.  They are share the same power and ground.  The routing is the least of your concerns I would venture.

 

If you really want isolation, turn them on one at a time.  If you want to see how one affects the other, turn on ring A, measure frequency, then turn on ring B, and measure again.  You may also create rings with non-harmonic lengths so they oscillate at unrelated frequencies.

Austin Lesea
Principal Engineer
Xilinx San Jose
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herand
Participant
Participant
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Registered: ‎07-24-2017

I see a recurring pattern here, everytime I mention ring-oscillators, people try to convince me it's a bad idea :D

 

You're right, isolation is something I already take into concern: Switch them on one by one, have a spatial margin in-between, I also use partial and full reconfiguration to isolate them from each other.

 

Still, let's say I didn't mention them: Is it possible to influence the routing such that I forbid the auto-router to use specific ressources?

 

Is there any more advanced documentation than UG904, maybe even explaining possible routing patterns between CLB and switchboxes or between switchboxes themselves?

 

Thanks in advance and sorry for the repetitive questions.

 

Kind regards,

herand

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austin
Scholar
Scholar
2,740 Views
Registered: ‎02-27-2008

Yes,

 

You may assign specific routes.  Through loc constrains you fix the basic element (DFF, LUT) esily, then using TCL commands you can fix the wires (much much harder).

 

Painful, fraught with difficulties.  Not a supported flow.  Between the TCL guide, and viewing your design in Vivado implemented schematic view, and some experimentation, I am sure you will figure it out.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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help1help
Newbie
Newbie
1,998 Views
Registered: ‎04-01-2018

h,

   I used to have the same questions about routing (e.g How to find the optimal node from the neighbor nodes in Assign Routing Model).I routing a special wire by trial and error is much more stupid than router.Now,I would like to ask if this wiring strategy has involved xilinx's intellectual property.

 

                                                                                      thanks

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