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stv0g
Observer
Observer
9,016 Views
Registered: ‎02-26-2016

Create multiple clock enables with different rates

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I am trying to create multiple periodic clock enables with a rate which is an integral multiple / fraction of a provided clock enable.

 

In the first place, I was asking myself if I could use a PLL or MMCM and using their CLOCKDIV settings to generate the clock enables.

 

But now i have doubts wether this is possible.

What do you think?

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muzaffer
Teacher
Teacher
17,395 Views
Registered: ‎03-31-2012
It's not advisable to use clock source to generate clock enables. Clock enables are data signals and they are timed differently from clock signals. Even if you managed to generate them by pll/mmcm, they will be marked as clock and treated differently.
It's better to generate the clock enable signals by logic computations. This also helps the case with 1 out of N cycle enables which have a 1/N duty cycle which pll/mmcms can't do with N > 2.
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muzaffer
Teacher
Teacher
17,396 Views
Registered: ‎03-31-2012
It's not advisable to use clock source to generate clock enables. Clock enables are data signals and they are timed differently from clock signals. Even if you managed to generate them by pll/mmcm, they will be marked as clock and treated differently.
It's better to generate the clock enable signals by logic computations. This also helps the case with 1 out of N cycle enables which have a 1/N duty cycle which pll/mmcms can't do with N > 2.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

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