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Explorer
Explorer
3,370 Views
Registered: ‎05-14-2017

Custom AXI IP with additional I/O ports: how to add I/O ports apart of AXI M/S interface ?

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Hello,

 

Once I create a custom AXI IP, I am trying to understand how do I add, from Vivado IP Packager, additional I/O ports to my IP.

 

From IP Packager, I can see I can add an interface and then map the Interface Logical Ports to IP's Physical ports, but I don't what to map ports to others, I would like to add them to the IP.

 

Example: suppose I have an AXI slave IP. After writing a certain value to one of its registers, I would like to toggle an output pin (could be a signal reset for another IP or anything else, no matter what). How do I do this ? Do I have to edit my custom AXI IP VHDL, xml and other related files ?

 

Thank you in advance for any suggestion.

Regards,

Simon

1 Solution

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Moderator
Moderator
5,577 Views
Registered: ‎11-09-2015

Re: Custom AXI IP with additional I/O ports: how to add I/O ports apart of AXI M/S interface ?

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Hi @simozz,

 

You can only modify your VHDL. The ports of the top level should correspond to the ports of your IP.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

4 Replies
Moderator
Moderator
5,578 Views
Registered: ‎11-09-2015

Re: Custom AXI IP with additional I/O ports: how to add I/O ports apart of AXI M/S interface ?

Jump to solution

Hi @simozz,

 

You can only modify your VHDL. The ports of the top level should correspond to the ports of your IP.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Explorer
Explorer
3,358 Views
Registered: ‎05-14-2017

Re: Custom AXI IP with additional I/O ports: how to add I/O ports apart of AXI M/S interface ?

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Great. Thank you @florentw.

 

Regards,

Simon

 

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Adventurer
Adventurer
515 Views
Registered: ‎02-09-2011

Re: Custom AXI IP with additional I/O ports: how to add I/O ports apart of AXI M/S interface ?

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I have a problem where I have added an input port to the top level VHDL using "Edit in IP Packager" but the port does not show up in the Block Design (when back to the main project level) nor the component.xml file.  There are no error messages and synthesis gives no errors.  Any ideas as to what might be happening?  This worked when editing a different block.

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Adventurer
Adventurer
415 Views
Registered: ‎02-09-2011

Re: Custom AXI IP with additional I/O ports: how to add I/O ports apart of AXI M/S interface ?

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I ended up having to edit the component.xml file to add the port, taking an educated guess on the formatting.  Seemed to work.

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