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Adventurer
Adventurer
504 Views
Registered: ‎04-11-2019

Custom UltraScale+ project implementation problem

Got a scripted module and implemented it in the project. Logical simulation was successful.
But when starting on a chip, the module works or doesn't work (I control by ILA), depending on the connection / disconnection of external modules.
The whole design is made in one Clock Domain from AXI Clock (pl_clk0) = 100 MHz, Implementation Strategy: Performance Retiming.
Timing report seems OK. Can you advise?

Timing_report.png
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8 Replies
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Explorer
Explorer
488 Views
Registered: ‎04-19-2018

 

"works/ doesn't work" - what is your definition of "working"? Even better, what exactly is the difference in behaviour and result that you observe?

"depending on the connection / disconnection of external modules" - what are those modules?

Please understand that without these details, all we know is you have a box A and boxes B, C and D and depending on the connections between them you get different results that you call "working" and "non working" and you expect a solution.

We are engineers, not psychics.

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Adventurer
Adventurer
434 Views
Registered: ‎04-11-2019

Actually problem related to the message related to block where I see the problem:

There are 4 register/latch pins with no clock driven by root clock pin: top_bd_i/ddsreg/U0/reg_ctl/inst/state_reg[0]/Q (HIGH)

It definitely indicates problem related to the clock I connected to the module or insight the block. My question's : should I constraint AXI clock delivered from zinq_ultra_ps(pl_clk0). ? I have never see Xilinx constrain it in an Examples ( ZCU102 for example).

 

 

 

 

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Voyager
Voyager
429 Views
Registered: ‎06-28-2018

Hi @olkhramus 

Constraints for Zynq PS clock outputs are automatically generated.

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Adventurer
Adventurer
415 Views
Registered: ‎04-11-2019

If I understood correctly any actions related to the AXI clock constraints not requested from my side.

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Explorer
Explorer
389 Views
Registered: ‎04-19-2018

 

You are not using combinational signals as clocks, are you?

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Adventurer
Adventurer
386 Views
Registered: ‎04-11-2019

No, all parts are clocked by AXI clock as a global clock. One Block where problems come from I don't control because it delivered as an encrypted but developer insist he doen't generate any clock inside. Only one strange thing in this module spec two input clocks are present : clk and clk x 2 that has to be phase aligned but according to the developer direction I connected both to the AXI clock. 

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Explorer
Explorer
380 Views
Registered: ‎04-19-2018

 

That smells fishy... an encrypted IP they say "oh, no, my IP doesn't do those things"

By the way, if you need to provide clocks at F and 2xF, how do you do that? I would generate them with an MMCM, they come out beautifully aligned.

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Adventurer
Adventurer
344 Views
Registered: ‎04-11-2019

both clock inputs connected to F due to IP developer directions. 

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