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esakki@babu
Explorer
Explorer
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Registered: ‎11-09-2018

DDR3 AXI DMA in Kintex KC705

I want to access DDR3 memory in Kintex KC705. I want to write arbitrary data in DDR3. I tried with IP block and I have following error during generating bitstream.   I attached my Block Design.  

example: arbitrary data 

reg [31:0] data_to_write = {32'hcafebabe};

 

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 119 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_diff_clock_0_clk_n, and sys_diff_clock_0_clk_p.

 

I have another question. How to write reg [31:0] data_to_write = {32'hcafebabe}; in DDR3 using MIG.

design_01.JPG
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syedz
Moderator
Moderator
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Registered: ‎01-16-2013

esakki@babu 

 

You need to define IOSTANDARD and PACKAGE_PIN constraints on sys_diff_clock_0_clk_n, and sys_diff_clock_0_clk_p ports mentioned in the error message. Check this AR: https://www.xilinx.com/support/answers/56354.html 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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syedz
Moderator
Moderator
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Registered: ‎01-16-2013

esakki@babu 

 

Can you share an update on this thread?

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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