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1,811 Views
Registered: ‎05-11-2017

[DRC 23-20] Rule violation CKLD-2

Hello, I'm JH.

 

I met some waring.

 

"WARNING: [DRC 23-20] Rule violation (CKLD-2) Clock Net has IO Driver, not a Clock Buf, and/or non-Clock loads - Clock net cin_clk is directly driven by an IO rather than a Clock Buffer or may be an IO driveing a mix or Clock Buffer and no n-Clock loads. This connectivity shoul be reviewed and corrected as appropiate. Driver: U_CVCLKIN/O."

 

xdc file,  "define_attibute {p:CDIN[11:0]} syn_useioff 1"

 

RTL is,

IBUFG U_CVCLKIN (.I(CVCLKIN), .O(cin_clk)); 

 

always @(posedge cin_clk or negedge RSTN) begin

      if(!RSTN) begin

        data <= 12'h0;

    end

    else begin

         data <= CDIN;

    end

end

 

How to solve this problem?

 

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7 Replies
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Moderator
Moderator
1,794 Views
Registered: ‎01-16-2013

Re: [DRC 23-20] Rule violation CKLD-2

@jeongho80.kim,

 

Can you open the schematic and check the connections of cin_clk? Check if the IBUFG is present at the clock.

Also check if the port is clock capable port.

 

--Syed

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Highlighted
Moderator
Moderator
1,721 Views
Registered: ‎01-16-2013

Re: [DRC 23-20] Rule violation CKLD-2

@jeongho80.kim,

 

Can you provide any update for this thread? Let us know if you have any more queries. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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Visitor
Visitor
1,253 Views
Registered: ‎08-20-2018

Re: [DRC 23-20] Rule violation CKLD-2

  • [DRC CKLD-2] Clock Net has IO Driver, not a Clock Buf, and/or non-Clock loads: Clock net clk_rst_gen/w_PCIe_refclk_bufg is directly driven by an IO rather than a Clock Buffer or may be an IO driving a mix of Clock Buffer and non-Clock loads. This connectivity should be reviewed and corrected as appropriate. Driver(s): clk_rst_gen/PCIe_refclk/O

Can someone help me with this warning?

Because of this my PCIe card is not getting detected in the system. Someone please help me with this.

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Visitor
Visitor
1,242 Views
Registered: ‎08-20-2018

Re: [DRC 23-20] Rule violation CKLD-2

I'm using VIVADO 2017.2. I had instantiated a IBUFGDS but in the schematic it's showing IBUFDS.

 

IBUFGDS #(
.DIFF_TERM ("TRUE"), // Differential Termination
.IBUF_LOW_PWR ("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD ("DEFAULT") // Specifies the I/O standard for this buffer
) PCIe_refclk (
.O (w_PCIe_refclk_bufg), // Clock buffer output
.I (i_PCIe_refclk_p), // Diff_p clock buffer input
.IB (i_PCIe_refclk_n) // Diff_n clock buffer input
);

ODDR #(
.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC")
) PCIe_refclk_p_0 (
.Q (o_PCIe_refclk_p[0]),
.C (w_PCIe_refclk_bufg),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (~board_reset_n),
.S (1'b0)
);

ODDR #(
.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC")
) PCIe_refclk_n_0 (
.Q (o_PCIe_refclk_n[0]),
.C (w_PCIe_refclk_bufg),
.CE (1'b1),
.D1 (1'b0),
.D2 (1'b1),
.R (~board_reset_n),
.S (1'b0)
);

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Highlighted
Xilinx Employee
Xilinx Employee
1,237 Views
Registered: ‎05-08-2012

Re: [DRC 23-20] Rule violation CKLD-2

Hi @jeongho80.kim. The IBUFG will need to be replaced by an IBUF + BUFG instantiation. The IBUFG was targeted for older architectures. For newer architectures (7-Series, UltraScale/UltraScale+) the IBUFG will only result in an I/O buffer IBUF. This would result in the CKLD-2 DRC.


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Visitor
Visitor
1,226 Views
Registered: ‎08-20-2018

Re: [DRC 23-20] Rule violation CKLD-2

After replacing IBUFGDS by an IBUF + BUFG instantiation, i'm getting the following Implementation error.

 

[Place 30-574] Poor placement for routing between an IO pin and BUFG.

[Place 30-99]Placer failed with error.'IO Clock Placer Failed'

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Xilinx Employee
Xilinx Employee
1,192 Views
Registered: ‎05-08-2012

Re: [DRC 23-20] Rule violation CKLD-2

Hi sharathm@535. Is the full message available to post as well as the full device name/part?  This will show what instances and physical sites are involved, and should show whether constraints are involved. The part will allow me to see the physical location of these relative to each other. The message should have a section such as below:

 

clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y248
and BUFG_inst (BUFG.I) is locked to BUFGCTRL_X0Y31

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