[DRC 23-20] Rule violation (NSTD-1) unspecified I/O standard ethernet lite zynq

[tsotnep2]

I'm using ZedBoard Zynq Evaluation and Development Kit (xc7z020clg484-1)

I want ethernet on baremetal application.

but i get the two error below when i add ethernet lite:

[DRC 23-20] Rule violation (NSTD-1) unspecified I/O standard

[DRC 23-20] Rule violation (UCIO-1) Unconstrained logical port

1. why do i get this error? should not be this data included in ethernet IP ? or i missed something somewhere?

2. is using those two commands safe? when they're not safe? p.s. it works but still: ref: http://www.xilinx.com/support/answers/56354.html

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

3. the link says LVCMOS18 and LVCMOS25 are the IO standards for 7 series. so they're practically about standard of operating voltage what does those letter mean? LVCMOS.

Unconstrained logical port means, i have to set the actual pin number ? on which pin this signal should be mapped?

Then for ethernet, I have to manually set them on the pins that are connected to ethernet port right? or i should hope if i ignore that(with command above) it will automatically do that?

thank you

[balkris]

check this ARs
http://www.xilinx.com/support/answers/56354.html

[muzaffer]

you need to assign the top level signals ie MDIO_RTL_MDC etc. to pins of the FPGA in your XDC file using PACKAGE_PIN constraints and also set the respective IOSTANDARD constraints for these pins.

Making these errors into warning is not enough as they will prevent a bitfile to be generated.

[tsotnep2]

Hi, thank you very much for response

so i'm trying to set those constraints.

mdio_rtl_mdc, 
mdio_rtl_mdio_io, 
mii_rtl_txd[3:0], 
mii_rtl_rxd[3:0], 
mii_rtl_crs, 
mii_rtl_rst_n, 
mii_rtl_rx_clk, 
mii_rtl_rx_dv, 
mii_rtl_rx_er, 
mii_rtl_tx_clk, 
mii_rtl_tx_en,

i manually opened : open_runs impl_1 

and tried setting them but got those errors:

set_property IOSTANDARD LVCMOS18 [get_ports {mdio_rtl_mdc}]
set_property PACKAGE_PIN D10 [get_ports {mdio_rtl_mdc}]
ERROR: [Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid

set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_txd[0]}]
set_property PACKAGE_PIN E9 [get_ports {mii_rtl_txd[0]}]
ERROR: [Vivado 12-1411] Cannot set LOC property of ports, 
Could not legally place instance mii_rtl_txd_OBUF[0]_inst at E9 (IOPAD_X1Y94) since 
it belongs to a shape containing instance design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[0].
TX_FF_I. The shape requires relative placement between mii_rtl_txd_OBUF[0]_inst and 
design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[0].TX_FF_I that can not be honoured because it 
would result in an invalid location for design_1_i/axi_ethernetlite_0/U0/IOFFS_GEN[0].TX_FF_I.

but usually i use this pre-bitstream tcl script:

#src of info : http://www.xilinx.com/support/answers/56354.html
set_property IOSTANDARD LVCMOS18 [get_ports {mdio_rtl_mdc}]
set_property IOSTANDARD LVCMOS18 [get_ports {mdio_rtl_mdio_io}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_txd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_txd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_txd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_txd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rxd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rxd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rxd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rxd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_crs}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rst_n}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rx_clk}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rx_dv}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rx_er}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_tx_clk}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_tx_en}]

#src of info 1 : http://dl.dropbox.com/u/65113214/16-10-05_23%3A49%3A52_Selection.png
    #taken from page 20-21 : http://zedboard.org/sites/default/files/documentations/ZedBoard_HW_UG_v2_2.pdf
set_property PACKAGE_PIN D10 [get_ports {mdio_rtl_mdc}]
#set_property PACKAGE_PIN C12 [get_ports {mdio_rtl_mdio_io}]
set_property PACKAGE_PIN E9 [get_ports {mii_rtl_txd[0]}]
set_property PACKAGE_PIN A7 [get_ports {mii_rtl_txd[1]}]
set_property PACKAGE_PIN E10 [get_ports {mii_rtl_txd[2]}]
set_property PACKAGE_PIN A8 [get_ports {mii_rtl_txd[3]}]
set_property PACKAGE_PIN E11 [get_ports {mii_rtl_rxd[0]}]
set_property PACKAGE_PIN B7 [get_ports {mii_rtl_rxd[1]}]
set_property PACKAGE_PIN F12 [get_ports {mii_rtl_rxd[2]}]
set_property PACKAGE_PIN A13 [get_ports {mii_rtl_rxd[3]}]
#set_property PACKAGE_PIN  [get_ports {mii_rtl_crs}]
#set_property PACKAGE_PIN  [get_ports {mii_rtl_rst_n}]
set_property PACKAGE_PIN A14 [get_ports {mii_rtl_rx_clk}]
#set_property PACKAGE_PIN  [get_ports {mii_rtl_rx_dv}]
#set_property PACKAGE_PIN  [get_ports {mii_rtl_rx_er}]
set_property PACKAGE_PIN D6 [get_ports {mii_rtl_tx_clk}]
#set_property PACKAGE_PIN  [get_ports {mii_rtl_tx_en}]


#disable warnings for those that had no pin locations specified in manual
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

same on vivado 2016.1

i think i might be making a simple mistake, i just want an ethernet working on baremetal... 

where do i set IP address and etc? in software?

[tsotnep2 · Accepted solution]

so i was super wrong in doing that. 

i was thinking maybe zynq processing system has ethernet included, and that is correct. no need to add ethernet lite ip separately