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Visitor amir.xilinx
Registered: ‎01-25-2018

DRC 23-20] Rule violation (NSTD-1)

hi evry body
i have a confuse error in generate for my project in vivado 16.4
when i add a I/O pin to my poject without used that, bit file is generaed but when used that(for example assaigned that to a signal for considered in ILA) bit file is not generated.this is the error message:
Vivado write_bitstream - ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - X out of Y logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value.

i used the solution 2 from the this link xilinx suport
Add tcl file to write bitstream setting in tcl.pre

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

The bitfile is generated but not work correctly the: added I/O pin not value in debug by ILA or consider if condition whereas its 2.5v on pin.
i used vc707 xilinx board and I/O pin added from fmc2

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2 Replies
Scholar dpaul24
Registered: ‎08-07-2014

Re: DRC 23-20] Rule violation (NSTD-1)



what I understand from it, the IOSTANDARD is missing for that used IO pin. Don't keep it to default.


In your xdc, use something like: set_property IOSTANDARD LVCMOS33 [ get_ports {your_io_pin_name}]


In the above it is LVCMOS33, but it can ve different for yours.

FPGA enthusiast!
All PMs will be ignored
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Visitor amir.xilinx
Registered: ‎01-25-2018

Re: DRC 23-20] Rule violation (NSTD-1)

Thnks for your replay
The XDC is correct, when is not assigned this pin to any another signal in archetect the bitfile generate completly but when assigned this pin another signal( for example ILA or a component) shows this error. its confuse for me
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