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xiaotong12
Newbie
Newbie
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Registered: ‎05-21-2016

[DRC 23-20] Rule violation (PLIDC-9) IDELAYCTRL DRC Checks...The REFCLK pin of a IDELAYCTRL instance should always be driven by clock buffer

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 I use VIVADO2015.03 and Virtex-7 mig ddr3 IP. During implementation, the error message is as follow:

 

ERROR: [DRC 23-20] Rule violation (PLIDC-9) IDELAYCTRL DRC Checks - REFCLK pin of IDELAYCTRL instance 'i_mig_ddr_controller/u_mig_mig/u_iodelay_ctrl/u_idelayctrl_200' is driven by 'clk200Mhz_ibuf'{IBUFDS}. This will lead to unroutable situation. The REFCLK pin of a IDELAYCTRL instance should always be driven by clock buffer

 

 

The clk200Mhz_ibuf is the clock of ddr3. Its funout is 2 and Vivado does insert BUFG for it during retarget phase of opt_design. But the place_design step through out the DRC error and ask for clock buffer. Is there any solution to eliminate the error?

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syedz
Moderator
Moderator
8,725 Views
Registered: ‎01-16-2013

@xiaotong12@shirley_yang,

 

Can you try to manually instantiate BUFG on clk200Mhz net in the RTL.

 

You can also try to use CLOCK_BUFFER_TYPE attribute on the clock clk200Mhz. Check page number 43 in below user guide:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug901-vivado-synthesis.pdf

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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shirley_yang
Observer
Observer
5,073 Views
Registered: ‎05-12-2016

Hi,

Is there any update info refer to this problem?

Thanks!

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syedz
Moderator
Moderator
8,726 Views
Registered: ‎01-16-2013

@xiaotong12@shirley_yang,

 

Can you try to manually instantiate BUFG on clk200Mhz net in the RTL.

 

You can also try to use CLOCK_BUFFER_TYPE attribute on the clock clk200Mhz. Check page number 43 in below user guide:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug901-vivado-synthesis.pdf

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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xiaotong12
Newbie
Newbie
5,035 Views
Registered: ‎05-21-2016

I remember we did try to manually insert BUFG in our code. You can try that. We changed a synthesis tool version (Protocompiler) now and seems there's no this issue.

 

Thanks,

Xiaotong

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