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Newbie lujiaqi
Newbie
1,344 Views
Registered: ‎01-25-2018

[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 152 net(s) are partially routed.

tool: vivado2015.2 FPGA: V7
Vivado Implementation fails to route my design completely. Below are some of the messages.

how to eliminate these errors?

 

[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 152 net(s) are partially routed.
The problem bus(es) and/or net(s) are
u0_eth_interface_top_PM/goo0[0].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2,
u0_eth_interface_top_PM/goo0[1].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_2,
u0_eth_interface_top_PM/goo0[0].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4,
u0_eth_interface_top_PM/goo0[1].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_4,
u0_eth_interface_top_PM/goo0[0].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5,
u0_eth_interface_top_PM/goo0[1].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_5,
u0_eth_interface_top_PM/goo0[0].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6,
u0_eth_interface_top_PM/goo0[1].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/pcs_top_i/rx_pcs_i/rxreset_6,
u0_eth_interface_top_PM/goo0[0].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2[7:0],
u0_eth_interface_top_PM/goo0[1].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/xgmii_txc_reg2[7:0],
u0_eth_interface_top_PM/goo0[0].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2[63:0],
u0_eth_interface_top_PM/goo0[1].u_xge_top/u_xge_mac_interface/u_xge_phy_core/U0/xge_phy_core_new_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/xgmii_txd_reg2[63:0].

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3 Replies
Scholar watari
Scholar
1,329 Views
Registered: ‎06-16-2013

Re: [DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 152 net(s) are partially routed.

Hi @lujiaqi

 

I'm not sure. But the following AR (#65502) is helpful for you.

 

https://www.xilinx.com/support/answers/65502.html

 

Best regards,

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Newbie lujiaqi
Newbie
1,194 Views
Registered: ‎01-25-2018

Re: [DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 152 net(s) are partially routed.

I'll try it ,thank you!

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Xilinx Employee
Xilinx Employee
1,183 Views
Registered: ‎05-08-2012

Re: [DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 152 net(s) are partially routed.

Hi @lujiaqi. Can the implementation log file be attached? I suspect congestion might be causing the routing failures, but a log would help to confirm. If this is the case, then the following answer record could help:

 

https://www.xilinx.com/support/answers/66314.html

 

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