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Visitor
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Registered: ‎11-14-2017

[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 4 net(s) are partially routed.

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Hi,all

tool: vivado2016.2 FPGA: ultrascale vitrex 440
Vivado Implementation fails to route my design completely. Below are some of the critical warning messages.

how to eliminate these critical warnings and errors?

[Route 35-54] Net: u_tp9001_wop/u_tp9001_cor/u_aproc/reset_axi_n_i is not completely routed.
[Route 35-54] Net: u_tp9001_wop/u_tp9001_cor/u_aproc/reset_aproc_cpu_n_i is not completely routed.
[Route 35-54] Net: u_tp9001_wop/u_tp9001_cor/u_arm_rng_top/u_rng_engine/u_rng_proc/u_prng_top/u_rng_tdes/des_rst_n_i is not completely routed.
[Route 35-54] Net: rst_n_pad_in is not completely routed.
[Route 35-54] Net: u_tp9001_wop/u_tp9001_cor/u_arm_rng_top/u_rng_engine/u_dxm_rst_logic/i_rst_n_gen/rst_n_i is not completely routed.
[Route 35-54] Net: u_tp9001_wop/u_img_acpu_top/u_acpu_axi2axi/aresetn_m_i is not completely routed.
[Route 35-54] Net: u_tp9001_wop/u_tp9001_cor/u_arm_rng_top/u_rng_engine/u_rng_proc/u_prng_top/u_rng_tdes/des_rst_n_i is not completely routed.
[Route 35-54] Net: rst_n_pad_in is not completely routed.
[Route 35-54] Net: u_tp9001_wop/u_tp9001_cor/u_arm_rng_top/u_rng_engine/u_dxm_rst_logic/i_rst_n_gen/rst_n_i is not completely routed.
[Route 35-54] Net: u_tp9001_wop/u_img_acpu_top/u_acpu_axi2axi/aresetn_m_i is not completely routed.
[Route 35-8] Design has 1334 unrouted pins, that are still reachable.
[Route 35-162] 4 signals failed to route due to routing congestion. Please run report_route_status to get a full summary of the design's routing. Below is a list of the top 10 physical nodes with signal overlaps and up to 5 of the signals that were contending for this node resource: Resolution: Run report_route_status to get a full summary of the design's routing. To find the areas of the congestion, use the route congestion Metrics in the Device View and check the logfile for the Congestion Report.
[Route 35-2] Design is not legally routed. There are 4 node overlaps. Resolution: Run report_design_analysis -congestion and -complexity to find potential sources of congestion in the areas where nets are not fully routed and review UG906 for design closure techniques.
[Route 35-1] Design is not completely routed. There are 4 nets that are not completely routed.
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
Write Bitstream
[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 4 net(s) are partially routed. The problem bus(es) and/or net(s) are u_tp9001_wop/u_img_acpu_top/u_acpu_axi2axi/aresetn_m_i, u_tp9001_wop/u_tp9001_cor/u_arm_rng_top/u_rng_engine/u_rng_proc/u_prng_top/u_rng_tdes/des_rst_n_i, u_tp9001_wop/u_tp9001_cor/u_arm_rng_top/u_rng_engine/u_dxm_rst_logic/i_rst_n_gen/rst_n_i, rst_n_pad_in.
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
attached route files
thanks
justin

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Moderator
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Registered: ‎01-16-2013

Re: [DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 4 net(s) are partially routed.

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@justinz,

 

It is hard to comment without looking at the connection of the net mentioned in the warning message. 

Open the implemented design and check the net connections of unrouted net,  Use the below AR as an initial reference point:

https://www.xilinx.com/support/answers/53854.html

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Registered: ‎01-16-2013

Re: [DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 4 net(s) are partially routed.

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@justinz,

 

From the log the unrouting looks to be due to congestion. Please check the following Links:

Congestion Answer Record: https://www.xilinx.com/support/answers/66314.html

Routing Debug: https://www.xilinx.com/support/answers/53854.html

Quick Take video: https://www.xilinx.com/video/hardware/how-to-resolve-routing-congestion.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Visitor
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Registered: ‎11-14-2017

Re: [DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 4 net(s) are partially routed.

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Hi ,syedz,
thank you for your suggestions. would you please give more detail suggestions about how to eliminate warning [route 35-54] in my design. replies of warning [route 35-54] in the forum are corresponding to different designs.
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Moderator
Moderator
4,394 Views
Registered: ‎01-16-2013

Re: [DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 4 net(s) are partially routed.

Jump to solution

@justinz,

 

It is hard to comment without looking at the connection of the net mentioned in the warning message. 

Open the implemented design and check the net connections of unrouted net,  Use the below AR as an initial reference point:

https://www.xilinx.com/support/answers/53854.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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