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Explorer
Explorer
8,238 Views
Registered: ‎07-18-2011

[DRC 23-20] Rule violation (RTSTAT-3) Unplaced terminals on net

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Hello,

 

I need help understanding why my design is failing DRC checks during the write_bitstream command:

 

[DRC 23-20] Rule violation (RTSTAT-3) Unplaced terminals on net - 12 net(s) have unplaced terminals.
The problem bus(es) and/or net(s) are
ch0_gthrxn_in,
ch0_gthrxp_in,
ch1_gthrxn_in,
ch1_gthrxp_in,
example_wrapper_inst/xusgth_1v5_10g_raw32_lc2_inst/inst/gen_gtwizard_gthe3_top.xusgth_1v5_10g_raw32_lc2_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[26].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthtxn_out[0],
example_wrapper_inst/xusgth_1v5_10g_raw32_lc2_inst/inst/gen_gtwizard_gthe3_top.xusgth_1v5_10g_raw32_lc2_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[27].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthtxn_out[0],
example_wrapper_inst/xusgth_1v5_10g_raw32_lc2_inst/inst/gen_gtwizard_gthe3_top.xusgth_1v5_10g_raw32_lc2_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[26].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthtxp_out[0],
example_wrapper_inst/xusgth_1v5_10g_raw32_lc2_inst/inst/gen_gtwizard_gthe3_top.xusgth_1v5_10g_raw32_lc2_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[27].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthtxp_out[0],
mgtrefclk0_x1y2_n,
mgtrefclk0_x1y2_p,
mgtrefclk0_x1y3_n,
mgtrefclk0_x1y3_p.

 

The design is placed, routed and meets timing.I'm running Vivado 2015.2.

 

Thanks,

David

 

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Explorer
Explorer
15,596 Views
Registered: ‎07-18-2011

Thanks for the reply. Indeed the GTH pins are not being connected to the GTH transceiver logic. It's very strange.

 

After playing around with this I believe the issue is related to the process of automatically updating a GTH core generated in 2015.1 to 2015.2. I recreated the core in the 2015.2 wizard (rather than upgrading) and I didn't run into this problem.

 

Thanks,

Dave

 

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2 Replies
Scholar
Scholar
8,206 Views
Registered: ‎06-05-2013

@david.hoffman RSTAT-3 checks unrouted and partially routed nets

Check log for detailed information.

 

open implemented design and look for buses and nets listed in drc.

-Pratham

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Highlighted
Explorer
Explorer
15,597 Views
Registered: ‎07-18-2011

Thanks for the reply. Indeed the GTH pins are not being connected to the GTH transceiver logic. It's very strange.

 

After playing around with this I believe the issue is related to the process of automatically updating a GTH core generated in 2015.1 to 2015.2. I recreated the core in the 2015.2 wizard (rather than upgrading) and I didn't run into this problem.

 

Thanks,

Dave

 

View solution in original post

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