03-01-2021 11:50 PM
For my application, I need to increase the depth of FIFO to 2^17 which is the max capacity of the FIFO generator. When I tried to generate bitstream for my project for the same FIFO depth, I get the following Implementation error.
I tried to look though the forums for anything that would help but some were verilog suggestions to define some macros which did not work. The error message suggests to "take steps to ensure placement of cascaded FIFO inside a single clock region" which I do not know how to.
Can someone suggest what can be done to solve this issue? I am using Vivado 2018.2 and FIFO Generator IP core 13.2
Thanks in advance,
03-07-2021 11:26 PM
Since FIFO Chain cannot span cross the clock region, the limitation of FIFO chain is 12.It's hardware limitation.
The IP generated in IP catalog has the fixed structure, which cannot be affected by the synthesis parameter.
I'm afraid the fifo structure has to be modified.