UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
1,545 Views
Registered: ‎11-27-2010

DRC Error with pins swapped

[DRC NSTD-1] Unspecified I/O Standard: 8 out of 74 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: rx_data_in_p[4], rx_data_in_p[3], rx_data_in_p[2], rx_data_in_p[1], rx_data_in_n[4], rx_data_in_n[3], rx_data_in_n[2], and rx_data_in_n[1].
[DRC UCIO-1] Unconstrained Logical Port: 8 out of 74 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: rx_data_in_p[4], rx_data_in_p[3], rx_data_in_p[2], rx_data_in_p[1], rx_data_in_n[4], rx_data_in_n[3], rx_data_in_n[2], and rx_data_in_n[1].
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

 

In this case, i DONT see any errors

set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ##
set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## 
set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## 
set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## 
set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## 
set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## 
set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## 
set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## 

 

in this case, i see errors [its just couple of pins swapped and no change in logic/anywhere else]

set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ##
set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## 
set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## 
set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## 
set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## 
set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## 
set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## 
set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ##

 

 

can anyone please explain why swapping causes above errors?

 

Thanks

 

 

DRC_error.png
0 Kudos
3 Replies
Voyager
Voyager
1,507 Views
Registered: ‎06-24-2013

Re: DRC Error with pins swapped

Hey @optivareddy,

 

can anyone please explain why swapping causes above errors?

Assuming that your differential ports are connected to something, they end up in a differential input buffer like for example IBUFDS. Now a differential buffer has two inputs, one for the true (_p) and one for the inverted (_n) input, and similar, each differential pin is either a master (_p) or a slave port (_n). Now if you connect them correctly, the tools will be happy and apply all your properties just fine but when you connect them the wrong way around, the following happens ...

CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, the positive port (P-side) 'rx_data_in_p[1]' of a differential pair cannot be placed on a negative package pin 'U10' (IOBS). 
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, the negative port (N-side) 'rx_data_in_n[1]' of a differential pair cannot be placed on a positive package pin 'T11' (IOBM). 
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, the positive port (P-side) 'rx_data_in_p[2]' of a differential pair cannot be placed on a negative package pin 'W10' (IOBS). 
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, the negative port (N-side) 'rx_data_in_n[2]' of a differential pair cannot be placed on a positive package pin 'W11' (IOBM). 
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, the positive port (P-side) 'rx_data_in_p[3]' of a differential pair cannot be placed on a negative package pin 'P10' (IOBS). 
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, the negative port (N-side) 'rx_data_in_n[3]' of a differential pair cannot be placed on a positive package pin 'P11' (IOBM). 
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, the positive port (P-side) 'rx_data_in_p[4]' of a differential pair cannot be placed on a negative package pin 'V9' (IOBS).
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, the negative port (N-side) 'rx_data_in_n[4]' of a differential pair cannot be placed on a positive package pin 'U9' (IOBM).

... and so, at the end of your build, you'll also get the Unconstrained Logical Port warnings.

 

Hope this clarifies,

Herbert

-------------- Yes, I do this for fun!
0 Kudos
Adventurer
Adventurer
1,479 Views
Registered: ‎11-27-2010

Re: DRC Error with pins swapped

Thanks,

           That helped me understand better.

 

 

0 Kudos
Voyager
Voyager
1,475 Views
Registered: ‎06-24-2013

Re: DRC Error with pins swapped

You're welcome!

 

All the best,

Herbert

-------------- Yes, I do this for fun!
0 Kudos