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Registered: ‎05-22-2018

[DRC REQP-1740] GTx R/TXOUTCLK drives invalid load: GTHE3_CHANNEL_PRIM_INST/RXOUTCLK should only drive a BUFG_GT load

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Hi everyone,

I am working with Vivado 2018.2. I trying to create a design that include JESD204_PHY and JESD204 IPs. When I try implementing the block design, I get the following errors.

[DRC REQP-1740] GTx R/TXOUTCLK drives invalid load: GTHE3_CHANNEL cell mySystem_i/JesdSubSys/jesd204_phy_0/inst/jesd204_phy_block_i/mySystem_jesd204_phy_0_0_gt_i/inst/
gen_gtwizard_gthe3_top.mySystem_jesd204_phy_0_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST pin mySystem_i/JesdSubSys/jesd204_phy_0/inst/jesd204_phy_block_i/mySystem_jesd204_phy_0_0_gt_i/inst/
gen_gtwizard_gthe3_top.mySystem_jesd204_phy_0_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK (net: mySystem_i/JesdSubSys/jesd204_phy_0/inst/jesd204_phy_block_i/mySystem_jesd204_phy_0_0_gt_i/
inst/gen_gtwizard_gthe3_top.mySystem_jesd204_phy_0_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/
rxoutclk_out[0]) should only drive a BUFG_GT load, but drives one or more invalid loads such as FDCE cell mySystem_i/JesdSubSys/leds_0/inst/forloop[4].in_cnt_reg[4][0].
Please insert a BUFG_GT between the GT and its load(s).


[DRC REQP-1740] GTx R/TXOUTCLK drives invalid load: GTHE3_CHANNEL cell mySystem_i/JesdSubSys/jesd204_phy_0/inst/jesd204_phy_block_i/mySystem_jesd204_phy_0_0_gt_i/inst/
gen_gtwizard_gthe3_top.mySystem_jesd204_phy_0_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST pin mySystem_i/JesdSubSys/jesd204_phy_0/inst/jesd204_phy_block_i/mySystem_jesd204_phy_0_0_gt_i/inst/
gen_gtwizard_gthe3_top.mySystem_jesd204_phy_0_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK (net: mySystem_i/JesdSubSys/jesd204_phy_0/inst/jesd204_phy_bloci/mySystem_jesd204_phy_0_0_gt_i/
inst/gen_gtwizard_gthe3_top.mySystem_jesd204_phy_0_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/
txoutclk_out[0]) should only drive a BUFG_GT load, but drives one or more invalid loads such as OBUF cell leds_OBUF[1]_inst.
Please insert a BUFG_GT between the GT and its load(s).

 

I am connecting the rxoutclk and txoutclk to LEDs. I try to use 'utility buffer' (in BUFG_GT mode) between the connections, but I still get the following error

 

[DRC REQP-1740] GTx R/TXOUTCLK drives invalid load: GTHE3_CHANNEL cell mySystem_i/JesdSubSys/jesd204_phy_0/inst/jesd204_phy_block_i/mySystem_jesd204_phy_0_0_gt_i/inst/
gen_gtwizard_gthe3_top.mySystem_jesd204_phy_0_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST pin mySystem_i/JesdSubSys/jesd204_phy_0/inst/jesd204_phy_block_i/mySystem_jesd204_phy_0_0_gt_i/inst/
gen_gtwizard_gthe3_top.mySystem_jesd204_phy_0_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/
gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK (net: mySystem_i/JesdSubSys/jesd204_phy_0/inst/jesd204_phy_block_i/mySystem_jesd204_phy_0_0_gt_i/
inst/gen_gtwizard_gthe3_top.mySystem_jesd204_phy_0_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[0].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/
rxoutclk_out[0]) should only drive a BUFG_GT load, but drives one or more invalid loads such as FDRE cell mySystem_i/JesdSubSys/jesd204_0/inst/rx_sysref_r_reg.
Please insert a BUFG_GT between the GT and its load(s).

 

 

Can someone tell me how to get through this?

 

Thanks in advance,

 

-Chandrasekhar DVS

 

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Moderator
Moderator
374 Views
Registered: ‎07-16-2008

Check the connection based on the error message.

Is FF "mySystem_i/JesdSubSys/jesd204_0/inst/rx_sysref_r_reg" driven by GT rxoutclk directly? If yes, change it to be sourced from BUFG_GT.

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Moderator
Moderator
375 Views
Registered: ‎07-16-2008

Check the connection based on the error message.

Is FF "mySystem_i/JesdSubSys/jesd204_0/inst/rx_sysref_r_reg" driven by GT rxoutclk directly? If yes, change it to be sourced from BUFG_GT.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

350 Views
Registered: ‎05-22-2018

Hi @graces ,

 

So I have used BUFG_GT between rxoutclk and all the ports it is directed to and that solved the issue!

 

Thank you,

 

-Chandrasekhar DVS

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