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276 Views
Registered: ‎05-27-2019

[DRC REQP-1975] OSERDES invalid clock topology

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Hi,

I get the following error message (targeting Pynq-Z2 board with XC7Z020CLG400-1 FPGA)

[DRC REQP-1975] OSERDES invalid clock topology: Unsupported clocking topology used for OSERDESE2 base_i/video/hdmi_out/frontend/rgb2dvi_0/U0/ClockSerializer/SerializerMaster. This can result in corrupted data. The base_i/video/hdmi_out/frontend/rgb2dvi_0/U0/ClockSerializer/SerializerMaster/CLK / base_i/video/hdmi_out/frontend/rgb2dvi_0/U0/ClockSerializer/SerializerMaster/CLKDIV pins should be driven by the same source through the same buffer type or by a BUFIO / BUFR combination in order to have a proper phase relationship. Please refer to the Select I/O User Guide for supported clocking topologies of the chosen INTERFACE_TYPE mode.

I'm using serialization ratio of 10 and get this error on both master and slave OSERDESE2 primitives. The topology seems to conform to Select I/O User Guide (ug471) since both CLK and CLKDIV inputs of OSERDESE2 are driven by a single MMCM without any phase shifts. Any suggestions?

Thanks,

Siamack

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232 Views
Registered: ‎01-22-2015

Re: [DRC REQP-1975] OSERDES invalid clock topology

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@s.beigmohammadi 

Welcome to the Xilinx Forum!

For a 10:1 DDR parallel-to-serial converter using the master and slave OSERDESE2 modules (see Fig 3-15 of UG471), I find that the following clocking avoids the DRC errors you are getting.
OSERDES_clocking.jpg

Note that the same type of clock buffer (I’ve used BUFG) should be placed on the CLK and CLKDIV outputs of the MMCM.  Also note for 10:1 DDR, that the frequency ratio, CLK:CLKDIV, is 5:1 (and not 10:1). 

Finally, the UG471 description of OSERDESE2.RST says that for both of the OSERDESE2 in your project, the RST pins should both be driven by the same reset net.  Further, the reset pins should be asserted asynchronously, and deasserted synchronously to CLKDIV.  That is, you should plan to use a reset synchronizer (eg. see XPM_CDC_ASYNC_RST in UG953).

Cheers,
Mark

3 Replies
233 Views
Registered: ‎01-22-2015

Re: [DRC REQP-1975] OSERDES invalid clock topology

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@s.beigmohammadi 

Welcome to the Xilinx Forum!

For a 10:1 DDR parallel-to-serial converter using the master and slave OSERDESE2 modules (see Fig 3-15 of UG471), I find that the following clocking avoids the DRC errors you are getting.
OSERDES_clocking.jpg

Note that the same type of clock buffer (I’ve used BUFG) should be placed on the CLK and CLKDIV outputs of the MMCM.  Also note for 10:1 DDR, that the frequency ratio, CLK:CLKDIV, is 5:1 (and not 10:1). 

Finally, the UG471 description of OSERDESE2.RST says that for both of the OSERDESE2 in your project, the RST pins should both be driven by the same reset net.  Further, the reset pins should be asserted asynchronously, and deasserted synchronously to CLKDIV.  That is, you should plan to use a reset synchronizer (eg. see XPM_CDC_ASYNC_RST in UG953).

Cheers,
Mark

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195 Views
Registered: ‎05-27-2019

Re: [DRC REQP-1975] OSERDES invalid clock topology

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markg@prosensing.com

Thanks for your answer. I tried BUFGs, but they limited the maximum frequency, so I switched to BUFR/BUFIO combination and that worked well. Thanks.

But why is it that some type of buffer is required? In section "OSERDESE2 Clocking Methods", UG471 states:

"There are several clocking arrangements within the FPGA to help the design meet the
phase relationship requirements of CLK and CLKDIV. The only valid clocking
arrangements for the OSERDESE2 are:
• CLK driven by BUFIO, CLKDIV driven by BUFR
• CLK and CLKDIV driven by CLKOUT[0:6] of the same MMCM or PLL"

So I assume it should be fine without any buffer.

Best,

Siamack

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185 Views
Registered: ‎01-22-2015

Re: [DRC REQP-1975] OSERDES invalid clock topology

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Siamack,

Clock outputs of the MMCM must be routed through a clock buffer in order to place the clocks into the FPGA clock tree.

For this and many other applications, using the “same type” of buffer on MMCM outputs will reduce clock skew and help the design pass timing analysis.

Mark