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mshin
Contributor
Contributor
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Registered: ‎02-14-2014

[DRC RTSTAT-3] : Why does this error happen?

Hello buddies,

During implementation of a design within a block design project containing microblaze/ddr/some other peripherals and in generating bitstream step, I encounter this. but why? and how to fix it?

 

[DRC RTSTAT-3] Unplaced terminals on nets: 46525 net(s) have unplaced terminals. The problem bus(es) and/or net(s) are i_system_wrapper/system_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Using_FPGA_4.of_read_ex_write_op1_conflict_INST2/A, i_system_wrapper/system_i/axi_timer/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_i_1_n_0, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_i_1_n_0, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_0, i_system_wrapper/system_i/axi_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_1, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_1, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_2, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_3, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_4, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_5, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_6, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_7, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_8, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_9, i_system_wrapper/system_i/axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg_reg_10... and (the first 15 of 41367 listed).
 

 

 

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dsheils
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Moderator
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Registered: ‎01-05-2017

Hi @mshin 

This DRC RTSTAT-3 checks the design for unrouted or partially routed nets. You will have to look at the Implementation log file to see what the list of nets are and what the reason is that they cannot be routed. You could use the -debug_log switch in route_design to get it to print more info. Also run report_route_status after route_design.

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mshin
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Registered: ‎02-14-2014

This is the output of "report_route_status" :

 

Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 166112 :
# of nets not needing routing.......... : 92272 :
# of internally routed nets........ : 91070 :
# of nets with no loads............ : 1202 :
# of routable nets..................... : 73840 :
# of fully routed nets............. : 73840 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

 

 

and the drc report file with regard to routing is attached.

 

I cannot find any reason or explanation in detail about that within these reports.

 

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syedz
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Moderator
134 Views
Registered: ‎01-16-2013

@mshin 

 

report_route_status shows the design is fully routed. Are you seeing any errors during bit file generation? Can you share the runme.log file from .runs/impl_1 folder?

If possible, try in the latest 2020.2 and check if you still see unplaced terminals. 

 

--Syed

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