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367 Views
Registered: ‎07-05-2019

DRC routing error

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Hello,

I am trying to implement the '7 series Integrated Block for PCI express' from IP integrator in Vivado 2019.2 for xc7z035fbg676-2. I am able to Synthesise and Implement the design. However during Bitstream generation, I am having the following error:

  • [DRC RTSTAT-1] Unrouted nets: 1 net(s) are unrouted. The problem bus(es) and/or net(s) are pcie_refclk_IBUF

I have the following constraint in .xdc file:

set_property PACKAGE_PIN R6 [get_ports pcie_refclk]

The refclk is mandatory to be connected to PIN R6.

Could you please help me with how the bitstream could be generated?

Thank you in advance for your reply,

Priya

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-30-2019

Hi priyankari.chevuturi@heitec.de 

Have a Look at the following AR, which discusses debugging and solving the routing issues in Vivado

https://www.xilinx.com/support/answers/53854.html

 

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Xilinx Employee
Xilinx Employee
302 Views
Registered: ‎01-30-2019

Hi priyankari.chevuturi@heitec.de 

Have a Look at the following AR, which discusses debugging and solving the routing issues in Vivado

https://www.xilinx.com/support/answers/53854.html

 

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232 Views
Registered: ‎07-05-2019

The real solution for my scenario was that there had to be differential clock input for the MGT clock. This can not be done with Create Port option. Hence adding a clock buffer would create a differentiual clock pair. 

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