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Observer multiprobe
Observer
10,188 Views
Registered: ‎06-26-2014

DRC violation REQP-1619 - IBUFDS_GTE2_driven_by_IBUF

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I am having a block diagram design,where I route an internal jitter attenuator clock(si5324) clock to my input clock ports, which are input to my custom logic.

The design synthesizes succesfully.I face the following error upon implementation:

"REQP-1619#1 Error
IBUFDS_GTE2_driven_by_IBUF
IBUFDS_GTE2 PS_plus_fabric_i/tengig_spi_0/inst/ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_shared_clock_reset_block/ibufds_inst pins I and IB should be driven by IBUFs."

 

Upon looking up at forum posts related to it, I edited the top level Verilog wrapper to add IBUF explicitly to each of these signals, and tried running with the edited wrapper. I can see the IBUFs initated in my elaborated design step, but they get dropped again during synthesis design step, and now I get the error:

 

"[Opt 31-38] IBUFDS_GTE2 PS_plus_fabric_i/tengig_spi_0/inst/ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_shared_clock_reset_block/ibufds_inst I pin is connected directly to a top-level port. An IBUF must be inserted in between the port and the IBUFDS_GT"

 

In what case will something be present in elaborated design but dropped from synthesized design ( I notice this in schematic view for both steps).

 

Can you help me fix the orginal error as well?

 

 

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1 Solution

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Xilinx Employee
Xilinx Employee
18,261 Views
Registered: ‎09-20-2012

Re: DRC violation REQP-1619 - IBUFDS_GTE2_driven_by_IBUF

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Hi,

 

Can you check if by any chance the wrapper is being regenerated during synthesis and your changes are lost?

 

Thanks,

Deepika.

Thanks,
Deepika.
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3 Replies
Xilinx Employee
Xilinx Employee
10,175 Views
Registered: ‎04-16-2012

Re: DRC violation REQP-1619 - IBUFDS_GTE2_driven_by_IBUF

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Hello @multiprobe

 

Can you try adding the DONT_TOUCH attribute on the instantiated IBUF and check whether it is dropped?

 

See the section "DONT_TOUCH" in the following user guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf 

 

Thanks,

Vinay

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Xilinx Employee
Xilinx Employee
18,262 Views
Registered: ‎09-20-2012

Re: DRC violation REQP-1619 - IBUFDS_GTE2_driven_by_IBUF

Jump to solution

Hi,

 

Can you check if by any chance the wrapper is being regenerated during synthesis and your changes are lost?

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Moderator
Moderator
10,150 Views
Registered: ‎01-16-2013

Re: DRC violation REQP-1619 - IBUFDS_GTE2_driven_by_IBUF

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Hi,

 

Can you share the attribute applied in RTL to infer IBUF and also the complete implementation log file?

 

--Syed

 

 

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Did you check our new quick reference timing closure guide (UG1292)?
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