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Explorer
Explorer
557 Views
Registered: ‎10-16-2018

DSP48e1 exceeds the device

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Hi ,

Kindly,

How I can modify the DSP chain to make it fit into my own device or the "SLR DSP column"? 

There is an attached snapshot for the error (Warning lead to implementation error). I tried to avoid this error by re-run implementation, but no way. 

By the way what is SLR stands for?

Thanks

SLR.JPG
SLR2.JPG
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1 Solution

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Highlighted
396 Views
Registered: ‎06-21-2017

Re: DSP48e1 exceeds the device

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This post https://forums.xilinx.com/t5/DSP-IP-and-Tools/Selecting-Filter-Architecture/m-p/984491 says that you have a 300 MHz system clock.  If you only have a 48KHz sampling rate you should be able to implement a hundred taps or so with four or 5 DSP slices.  The FIR compiler will do this for you. 

If you really need a large bandpass FIR filter with a sampling rate equal to the system clock rate, you could always break it into a high pass filter and a low pass filter.  If your pass band is close to the middle of the spectrum, the number of taps you need for each filter should be roughly equal.  You will probably need to insert a couple pipeline registers between the two filters to get the data back across the chip to the second filter section to make timing at a high system clock frequency.

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14 Replies
Xilinx Employee
Xilinx Employee
545 Views
Registered: ‎05-22-2018

Re: DSP48e1 exceeds the device

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Hi @ahmed_alfadhel ,

Please check this AR# link:

https://www.xilinx.com/support/answers/71765.html

Thanks,

Raj

Explorer
Explorer
537 Views
Registered: ‎10-16-2018

Re: DSP48e1 exceeds the device

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Hi @rshekhaw ,

When I enetered the TCL command :

set_param logicopt.enableDSPCascadeFixing false

I got:

ERROR: [Common 17-153] Param 'logicopt.enableDSPCascadeFixing' does not exist

,

what I can do with this , any ideas? 

Thanks.

TCL.JPG
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Moderator
Moderator
487 Views
Registered: ‎11-04-2010

Re: DSP48e1 exceeds the device

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Hi, @ahmed_alfadhel ,

The paramter only exists in the Vivado 2018.3 and the version new than 2018.3.

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Xilinx Employee
Xilinx Employee
449 Views
Registered: ‎05-08-2012

Re: DSP48e1 exceeds the device

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Hi @ahmed_alfadhel 

What version of Vivado is being used? There are likely different options based on the version.


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Explorer
Explorer
442 Views
Registered: ‎10-16-2018

Re: DSP48e1 exceeds the device

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Hi @marcb ,

Vivado 2018.2 ,

I am looking forward yuor solution.

Thanks.

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Highlighted
397 Views
Registered: ‎06-21-2017

Re: DSP48e1 exceeds the device

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This post https://forums.xilinx.com/t5/DSP-IP-and-Tools/Selecting-Filter-Architecture/m-p/984491 says that you have a 300 MHz system clock.  If you only have a 48KHz sampling rate you should be able to implement a hundred taps or so with four or 5 DSP slices.  The FIR compiler will do this for you. 

If you really need a large bandpass FIR filter with a sampling rate equal to the system clock rate, you could always break it into a high pass filter and a low pass filter.  If your pass band is close to the middle of the spectrum, the number of taps you need for each filter should be roughly equal.  You will probably need to insert a couple pipeline registers between the two filters to get the data back across the chip to the second filter section to make timing at a high system clock frequency.

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Explorer
Explorer
372 Views
Registered: ‎10-16-2018

Re: DSP48e1 exceeds the device

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Hi @bruce_karaffa ,

You said: "If you only have a 48KHz sampling rate you should be able to implement a hundred taps or so with four or 5 DSP slices". 

I was don't know about this. 

In fact, the sampling frequency was set to 200 MHz since the Vivado Simulator doesn't veiw the output sinewave (DDS output) with correct timing when I used low sampling frequency ! 

For example when I reconfigured the sampling frequency to 50 kHz the Simulator vewied the sinewave (24 kHz) as follow :24kHz_Fs50kHz.JPGT = 2666 us

While, when I set the Fs to 200 MHz , the Simulator veiwed the output sinewave (24 kHz) with correct timng , as shown below:

 

24kHz_Fs200MHz.JPGT = 41 us

Looking forward your comments about this phenomenon .

 I attached the a snapshot for the testbench below:sim_code.JPG

Thanks.

 

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356 Views
Registered: ‎06-21-2017

Re: DSP48e1 exceeds the device

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Simply changing the Input Sampling Frequency in the FIR Compiler does not change how fast samples are entering your filter.  You must control this with the s_axis_data_tvalid signal.  All the Input Sampling Frequency parameter does is tell the FIR Complier how many clock cycles it has to process each sample.  If you want your filter to sample at 48KHz, you must set set s_axis_data_tvalid high for one clock cycle every 20.8333 microseconds (1/48000).  You need to create a signal to do this. You can use the 20.8333uS signal as the filter's s_axis_data_tvalid input.

One other suggestion.  Collect the input data to your filter and the output data.  Do FFTs to see where that noise is generated.

FYI, I'm looking at one of my filters with a 200MHz system clock frequency, 95 taps, 700KHz sampling frequency 16 bit coefficients and 32 bit input data.  It requires 5 DSPs.

Explorer
Explorer
349 Views
Registered: ‎10-16-2018

Re: DSP48e1 exceeds the device

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Thank you @bruce_karaffa  for your rich comments ! 

@bruce_karaffa wrote:

 " If you want your filter to sample at 48KHz, you must set set s_axis_data_tvalid high for one clock cycle every 20.8333 microseconds (1/48000). "


According to Vivado Simulator , TVALID that is comming out the DDS compiler into FIR compiler is always High. Does this lead to a problem if TVALID is always High ?

If yes, how to make TVALID is High only for one clock cycle? I mean I cannot manipulate the HDL of DDS compiler IP block.

Thanks.

 

 

 

TValid.JPG
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331 Views
Registered: ‎06-21-2017

Re: DSP48e1 exceeds the device

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If the filter's s_axis_data_tvalid signal is always high, it is taking samples at the system clock rate.  Try driving s_axis_data_tvalid with a counter based signal if you don't have anything in your system toggling at your sample clock rate yet.  Something like this.  Note that I'm at home so this is completely untested.

Constant Rollover  : unsigned(19 downto 0) := to_unsigned(<system clock freq>/<sample clock freq, 20);
Signal SampleCounter   : unsigned(19 downto 0) := (OTHERS => '0');
Signal s_axis_data_tvalid   : std_logic  := '0';

begin
process (SysCLK) 
begin
  if rising_edge(SysCLK) then
     s_axis_data_tvalid <= '0';
     if (SampleCounter = Rollover) then
        SampleCounter <= (OTHERS => '0');
       s_axis_data_tvalid <= '1';
    else
      SampleCounter   <= SampleCounter  + 1;
    end if;
  end if;
end process;
Explorer
Explorer
249 Views
Registered: ‎10-16-2018

Re: DSP48e1 exceeds the device

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Hi @bruce_karaffa ,

In order to control the TVALID signal I built my own IP core for impulse generation. I run the Vivado simulation for the new system design, but I don't know how to veiw the impulse response !?

 VHDL code for IP core inpulse generator:

----------------------------------------------------------------------------------------
-- Engineer: Ahmed Alfadhel
-- 
-- Create Date: 06/19/2019 09:46:48 PM
-- Design Name: 
-- Module Name: Impulse - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: Clk = 200 MHz
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Impulse is
    Port ( clk : in STD_LOGIC;
           impulse_data : out STD_LOGIC_VECTOR (7 downto 0);
           Valid : out STD_LOGIC;
           Ready : in STD_LOGIC);
end Impulse;

architecture Behavioral of Impulse is

signal o_impulse    : std_logic_vector(7 downto 0) := X"00";
signal s_Valid    : std_logic := '0';
constant maxcount  : integer := 4000;

begin
   impulse_data <= o_impulse;
   Valid <= s_Valid;
   LFSR_proc: process(clk)
   
    variable counter: unsigned(14 downto 0) := to_unsigned(0, 15);
    
   begin
     if(rising_edge(clk)) then
        
        counter := counter +1;
        
          if (counter = maxcount) then
            o_impulse <= X"40";
            s_Valid <= '1';
            counter := (others => '0');
          else
            o_impulse <= X"00";
            s_Valid <= '0';
          end if;
     end if;
   end process LFSR_proc;

end Behavioral;

I attached snapshots for the simulation. The second snapshot is just a zoom out for the first one. 

Kindly, I want to learn how to veiw the impulse response for the FIR filter I am using.  

Thanks.

simulation3fir.JPG
simulation4fir.JPG
Sys_design.JPG
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245 Views
Registered: ‎06-21-2017

Re: DSP48e1 exceeds the device

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Explorer
Explorer
220 Views
Registered: ‎10-16-2018

Re: DSP48e1 exceeds the device

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Hi @bruce_karaffa ,


@bruce_karaffa wrote:

FYI, I'm looking at one of my filters with a 200MHz system clock frequency, 95 taps, 700KHz sampling frequency 16 bit coefficients and 32 bit input data.  It requires 5 DSPs.


According to the your post here, you said I have to set the sampling frequency equals to or higher than the FIR clocking rate . Doesn't that seems contradictory to the written above !?

Thanks.


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Registered: ‎06-21-2017

Re: DSP48e1 exceeds the device

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No.  I said that you must set the sampling frequency in the FIR Compiler GUI equal to or higher than the rate that you are entering data into your filter.  The tvalid signal is what enters data into the filter.  A high system clock frequency generally leads to lower resource usage in the compiler.  If you are sampling at say 100KHz, you must set the sampling frequency to 100KHz ir higher.  If you are setting tvalid high for one clock cycle periodically, setting it to exactly 100KHz is OK.  If your input is bursty, you can either set the sampling frequency higher or smooth out the sampling rate with a FIFO before entering into the filter. 

You want a reasonably high system clock rate.  For an Artix on a fairly full design, I would try something between 100MHz and 200MHz.  You might be able to go higher, but you might run into timing problems.