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Observer
Observer
1,407 Views
Registered: ‎11-14-2017

Data and Clock out

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Hi all,

I'd like to understand a simple thing about the FPGA's output buffers and internal logic.  My project is very easy:

PIPO.png

 

This is what I have in my design block. I need to send this clock_out and data_out to another FPGA (or generic board) who receives these signal with Tsetup and Thold requirements and store data in example logic. With "clock create" command constraint I specify that clock_out is a clock, so inside the FPGA data_in and data_out are well-syncronized with clock_out. Now I write the pin constraints choosing a clock capable pin for clk_out, possibly in the same bank of data_out and without specify any kind of buffer (but directly connecting it to the pin of the package). 

My questions is: what do it happen after the output FPGA pad? Are still the electric signal data_out on FPGA pads well-syncronized with clock_out? If no, is there a command or a procedure to do it?

Thanks in advance, 

Gianmarco Borri

 

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Observer
Observer
1,383 Views
Registered: ‎11-14-2017

Re: Data and Clock out

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Hi dpaul,

thanks for the quick reply. I have two questions about this: 

1)So use an ODDR to forward the clock out of the FPGA. Use the Xilinx primitive ODDR instantiation.

I opened the schematic netlist and i saw the default buffer will be implemented is OBUF_inst. Should i add ODDR in design block before this buffer?

2) In the receiving FPGA you need to adjust your logic such that data_out and clock_out are in sync, even if they go out of sync while transmission.

What should I do if I've got a generic unprogrammable device with timing requirements and not a FPGA?

 

Thanks in advice,

Gianmarco Borri

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Scholar
Scholar
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Registered: ‎08-07-2014

Re: Data and Clock out

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@gianmarcoborri,

 

My questions is: what do it happen after the output FPGA pad? Are still the electric signal data_out on FPGA pads well-syncronized with clock_out?

 

Don't worry much about it. Your primary concern would be how to correctly forward the clock from one FPGA and how to correctly receive this same clock and data in another FPGA.

 

So use an ODDR to forward the clock out of the FPGA. Use the Xilinx primitive ODDR instantiation.

In the receiving FPGA you need to adjust your logic such that data_out and clock_out are in sync, even if they go out of sync while transmission.

 

 

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Observer
Observer
1,384 Views
Registered: ‎11-14-2017

Re: Data and Clock out

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Hi dpaul,

thanks for the quick reply. I have two questions about this: 

1)So use an ODDR to forward the clock out of the FPGA. Use the Xilinx primitive ODDR instantiation.

I opened the schematic netlist and i saw the default buffer will be implemented is OBUF_inst. Should i add ODDR in design block before this buffer?

2) In the receiving FPGA you need to adjust your logic such that data_out and clock_out are in sync, even if they go out of sync while transmission.

What should I do if I've got a generic unprogrammable device with timing requirements and not a FPGA?

 

Thanks in advice,

Gianmarco Borri

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Moderator
Moderator
1,242 Views
Registered: ‎01-16-2013

Re: Data and Clock out

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@gianmarcoborri,


Can you share which device are you using so that I can move your post to the correct board for a better response?

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Moderator
Moderator
1,174 Views
Registered: ‎01-16-2013

Re: Data and Clock out

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@gianmarcoborri,

 

This topic is still open and is waiting for you.

 

If your question is answered and/or your issue is solved, please mark a response that resolved your issue, as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions). This way, the topic can be completed then. 

 

If this is not solved/answered, please reply to the thread.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Observer
Observer
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Registered: ‎11-14-2017

Re: Data and Clock out

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Hello Syed,

sorry for the late. I didn't see your answer. Anyway, my board is ZC706 which mounts Zynq-7 FPGA.

I understand the dpaul's reply: after clock and data transmission, they will go out-of-sync in each case. My problem is that the receiver is a board with a fixed IC, and not a FPGA. I resolved this issue with a trial & error phase shifting of the clk_out.

Thanks for your replies.

Gianmarco Borri

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