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Visitor maanrl
Visitor
2,167 Views
Registered: ‎06-14-2011

Data2mem for Virtex-6 problem

Hi,

 

I'm working with a Virtex-6 (xc6vlx240t), I'm trying to use data2mem to replace the content of several BRAM blocks in my design, NGDBuild doesn't complain about my .bmm file so I assume the names for the RAM blocks are correct, however when Bitgen produces the top_bd.bmm file it doesn´t contain the PLACED keywords, instead the file produced is an exact copy (with some comments) of my original .bmm file, and therefore data2mem complains. Does anybody know why the top_bd.bmm is not being generated correctly?

 

I checked with the FPGA editor and the names forthe blocks have changed, for example:

 

Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_31

 

was subtituted with:

 

Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_31/RAMB16

 

If I have to use these new names in a new .bmm file then how do I tell Bitgen to ignore the previous .bmm file and use the new one?

 

 

This is the contents of my .bmm fil:

 

    ADDRESS_SPACE plasma_master RAMB16 [0x0000:0xFFFF]
        BUS_BLOCK
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_31 [31:31];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_30 [30:30];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_29 [29:29];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_28 [28:28];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_27 [27:27];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_26 [26:26];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_25 [25:25];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_24 [24:24];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_23 [23:23];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_22 [22:22];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_21 [21:21];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_20 [20:20];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_19 [19:19];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_18 [18:18];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_17 [17:17];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_16 [16:16];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_15 [15:15];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_14 [14:14];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_13 [13:13];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_12 [12:12];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_11 [11:11];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_10 [10:10];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_9 [9:9];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_8 [8:8];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_7 [7:7];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_6 [6:6];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_5 [5:5];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_4 [4:4];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_3 [3:3];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_2 [2:2];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_1 [1:1];
            Inst_HEMPS/Plasma_master_00/MASTER_RAM.RAM_RTL.u2_ram/ram_bit_0 [0:0];
        END_BUS_BLOCK;
    END_ADDRESS_SPACE;

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