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Explorer
Explorer
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Registered: ‎02-27-2018

Define ports as LVDS

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Hello,

 

I have a design and most of the entry ports are the outputs of an ADC these outputs are LVDS.

My question is how do i declare the inputs of my FPGA as LVDS signals?

For the moments in the design i just declared the inputs as std_logic_vector.

I don't know if the LVDS declaration has to be done in the syntesis step or the implementation?

Thank you for your help

lvdsports.png
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Moderator
Moderator
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Registered: ‎01-16-2013

@lebowski,

 

You will find them in language templates in Vivado. (Select Tools--> Language Template) 

 

Capture.JPG

 

Library UNISIM;
use UNISIM.vcomponents.all;

 

--Syed

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Moderator
Moderator
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Registered: ‎01-16-2013

@lebowski

 

Differential input and output buffers must be instantiated in your code as an IBUFDS or an OBUFDS.  They can not be inferred.  Your top level port declaration most include both a P and N port to connect to the IBUFDS I and IB ports or the OBUFDS O & OB ports.    The output port from the IBUFDS and the input port from the OBUFDS would be a single std_logic signal.

 

Source: https://forums.xilinx.com/t5/Welcome-Join/LVDS-differential-pairs-for-ISE-14-4-and-the-Spartan-3E/td-p/302571 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Explorer
Explorer
1,426 Views
Registered: ‎02-27-2018

Thank you, but the link doesn't work

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Moderator
Moderator
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Registered: ‎01-16-2013

@lebowski,


Check these: 

https://forums.xilinx.com/t5/Welcome-Join/LVDS-differential-pairs-for-ISE-14-4-and-the-Spartan-3E/m-p/302577

 

https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Differential-Signal-and-LVDS/td-p/36963

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Explorer
Explorer
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Registered: ‎02-27-2018

Which library should i use to use these components?

  IBUFDS_inst : IBUFDS
   generic map (
      DIFF_TERM => FALSE, -- Differential Termination
      IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD => "DEFAULT")
   port map (
      O => O,  -- Buffer output
      I => I,  -- Diff_p buffer input (connect directly to top-level port)
      IB => IB -- Diff_n buffer input (connect directly to top-level port)

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Moderator
Moderator
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Registered: ‎01-16-2013

@lebowski,

 

You will find them in language templates in Vivado. (Select Tools--> Language Template) 

 

Capture.JPG

 

Library UNISIM;
use UNISIM.vcomponents.all;

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post