Deriving a slow clock

[rcinmo]

I need a slow clock and can't get it from the DCM as the other needed frequencies won't allow.  I have a 64 bit register that is clocked at 250Mhz that I'd like to use the register[20] output to clock a process but the build process gives a gated clock warning.   

assign SlowClock = register[20];

always @(posedge SlowClock) 

While it works I'd like to know how to implement using a register output as a clock source in the fabric correctly?

ISE 14.4      XC6VLX550T

Thanks

[muzaffer]

If you'd been using Vivado I'd suggest adding a create_generated_clock constraint and let the tool to time it. It's been a while and I am not sure if there is a robust equivalent constraint in ISE to do this.

Another solution is the do a single cycle clock enable which coincides with the slowclock posedge and use it with the fast clock. This gets rids of all timing constraint issues and allows you to use a single clock in all your design.

[avrumw]

Generally, you don't use a fabric generated signal as a clock.

If you want to generate a clock you should use the resources provided for generating clocks. As you found out, the MMCM and DCM have limits to how slow they can go, so you need to use "other" dedicated clocking resources.

The best way to clock something at a very slow rate is to use a clock enable as @muzaffer suggested, or to use a BUFGCE or BUFHCE to generate a decimated clock.

The BUFGCE and BUFHCE allow you to "enable" a clock going through. So to get one of the same frequency as you want, you would assert an enable when all 21 bits of your counter are at a specific value (if you are counting up, usually 21'h1fffff) - this would let one clock pulse through the BUFGCE/BUFHCE. This would give you the frequency you want - but you need to be aware that it does not have a normal duty cycle, so you can't use the negative edge of the clock (either internally on a negedge, or on an ODDR/IDDR).

The attached pictures show how you use these cells...

Once you have created these clocks, they or the paths clocked on them should be constrained. You mentioned a DCM, so I assum you are using ISE (not Vivado). In ISE, you would need to create a group for all clocked elements that are clocked on this domain, and use a FROM TO. Assuming your 250MHz clock is constrained by the PERIOD timespec TS_clk250, then the constraints would be

NET slowClk TNM = tnm_slowClk;
TIMESPEC TS_slowClk = FROM tnm_slowClk TO tnm_slowClk TS_clk250 * 2097152;

(2097152 is 2^21)

[EDIT: See this post for a discussion on how to constrain a BUFGCE generated clock in Vivado]
[EDIT: See this post for using the CLOCK_DELAY_GROUP in UltraScale/UtraScale+]

Avrum

[gszakacs · Accepted solution]

Actually the way you're generating the clock could be OK as long as you understand how it works.  Unlike the diagrams that Avrum posted, your code just places another BUFG on the output of your register, which in turn drives the slow logic.  As I said, this is OK but only as long as you understand that this clock has significant delay from the 250 MHz clock that created it, so you can't expect a clean clock crossing from other signals generated with the 250 MHz clock into the slow clock domain, and vice versa.  Also the tools will not generally figure out the relationship between clocks like this and automatically compute setup and hold timing, so you need to consider them unrelated.  If the logic running on this slow clock has no real connections to logic in the 250 MHz domain, e.g. if you're just using it to blink LEDs, then you don't need to worry about it.

[hrmt]

Hi @avrumw and other guys

avrumw said : " Once you have created these clocks, they or the paths clocked on them should be constrained. You mentioned a DCM, so I assum you are using ISE (not Vivado). In ISE, you would need to create a group for all clocked elements that are clocked on this domain, and use a FROM TO. Assuming your 250MHz clock is constrained by the PERIOD timespec TS_clk250, then the constraints would be

NET slowClk TNM = tnm_slowClk;

TIMESPEC TS_slowClk = FROM tnm_slowClk TO tnm_slowClk TS_clk250 * 2097152; "

if we use bufgce method in vivado, what would be constraints?

[syedz]

@hrmt

Please create a new forum thread in Timing board for better responses. 

https://forums.xilinx.com/t5/Timing-Analysis/bd-p/TIMEANBD

--Syed

[avrumw]

if we use bufgce method in vivado, what would be constraints?

I have edited the original post to have a link to a different post that shows how to constrain BUFGCE generated clocks in Vivado.

Avrum

[avrumw]

if we use bufgce method in vivado, what would be constraints?

[hrmt]

@avrumw

when i clicked your link this page was shown : 

[avrumw]

@hrmt,

when i clicked your link this page was shown : 

Sorry - the link in the original post was correct, but the one in the later one was wrong - I have fixed it.

Avrum