08-07-2013 07:00 AM
I am having trouble with my Xilinx tools.
I have the full design suite license through the Xilinx Alliance program.
I am using:
Release Version: 14.5(nt)
Application Version : P.58f
I am implementing my design but after implementation has passed the Translation Report, Map report, Place and Route Report, Post-PAR Static Timing report will not update as well as the Design summary report. The reports seem to be stuck on Synthesized.
See attachment below.
Does anyone know how to fix this?
08-07-2013 07:53 AM
Try closing Design Summary window and open the design sumary from Project menu --> Design Summary/Reports
08-07-2013 06:42 PM
Check this AR out.
08-08-2013 07:53 AM
Yes that appears to be what is happening... I switch top Modules and synthesize and implement and the tools get lost and eventually the tools get lost.
08-16-2013 01:38 AM
In the process tab you have an option to clean up the project files . Do the clean up of your project file . Then try out the synthesis . This will solve the issue .