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Visitor
Visitor
346 Views
Registered: ‎10-07-2019

Design is not routable as its congestion level is 6

Hi all,

I am using Xilinx System generator to build an ip and Vivado 2018.3 to implement it on RFSoC ZCU1275 board. However, I received an error saying design is not routable as the congestion level is 6.

Therefore, I changed the implementation strategy to Congestion_SpreadLogic_high. However the issue still persists.

I have attached a screenshot of the error message, portion of the log and the block design here with. Can someone help me with this?

Thank you!

NJError MessageError MessageBlock designBlock designImplementation SettingsImplementation SettingsLogLog

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5 Replies
Xilinx Employee
Xilinx Employee
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Registered: ‎02-27-2019

回复: Design is not routable as its congestion level is 6

You can refer to https://www.xilinx.com/support/answers/66314.html . Congestion is a complex issue, sometimes you have to modify your design.

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Xilinx Employee
Xilinx Employee
299 Views
Registered: ‎05-22-2018

Re: Design is not routable as its congestion level is 6

Hi @najathakram ,

Also as the congestion level is of 6, you can try different sets of directives in each phase of implementation and try running multiple implementation runs. 

Also if you want it to be checked at our end, you can share the post place dcp.

Accordingly i will arrange the secure EZMove package.

Thanks,

Raj.

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Visitor
Visitor
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Registered: ‎10-07-2019

回复: Design is not routable as its congestion level is 6

Thank you very much. I am doing some changes to the design and, let me try a simplified version. 

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Visitor
Visitor
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Registered: ‎10-07-2019

Re: Design is not routable as its congestion level is 6

Hi Raj,

Thank you very much for the kind response. I would really appreciate if you could help me with this. However, I am not familiar with running multiple implementation runs at different implementation phases. I simply set the implementation strategy and tried running that. I have tried few other options, yet they didn't work. Could you please guide me through that?

I have added implementation files in this folder. 

https://www.dropbox.com/sh/wekuxpbt7l513ps/AACaG2F1F2EUveH-GTQMoH3ia?dl=0

Thank you very much!

Najath

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Xilinx Employee
Xilinx Employee
216 Views
Registered: ‎05-08-2012

Re: Design is not routable as its congestion level is 6

Hi @najathakram 

Taking a look at the utilization, many of the resources are not very utilized such as the LUTs (7%) and FFs (16). However, the DSPs are greatly over-utilized at 86.89 percent. This means a large number of bus nets using local resources. This can be seen by enabling the Vertical Routing Congestion metrics from the device view, which look to follow the DSP sites.

I would try moving many of these to other logic resources. To do so, the synth_design argument "-max_dsp 3000" can be used. This should put the DSPs at around 70 percent.

I would also suggest running the report_clock_interaction report and addressing the paths with no common clock marked as "Timed (unsafe)". This will not help the implementation QOR.

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