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cloukas
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Registered: ‎12-16-2018

Designutils 12-1133 error during implementation

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I have a project that I know for a fact that is working, since I have tested it on the ZCU102 board. To speed things up, I run Synthesis and Implementation in a university server.

I use some custom IPs, made in Vivado HLS with a target clock frequency of 250 MHz. I have successfully tested the design on the board for a clock frequency of 100 MHz and 150 MHz. At 200 MHz there were some minor timing violations, which were resolved by changing the implementation strategies. At the target frequency of 250 MHz however simply changing strategies did not work.

So I synthesized the custom IPs for a target frequency of 300 MHz, which I knew they could handle and surely enough HLS managed to synthesize them for 300 MHz. Then I used the new IPs on the design with a 250 MHz clock.

During the Implementation run, the server disk maxed out which resulted in an error. I canceled the process and reset all output products. The since then things have cleared up at the server, so I started the Synthesis and Implementation runs from scratch. However, Implementation did not finish. Instead I got the following error messages:

[Designutils 12-1133] Could not create routed site for BUFCE_LEAF_X290Y18

[Designutils 12-1133] Could not create routed site for BUFCE_LEAF_X424Y8

[Designutils 12-1133] Could not create routed site for BUFCE_LEAF_X425Y9

[Common 17-69] Command failed: Bitgen failed

I have no components or signals with the aforementioned names in the design and could not locate the source of these errors. Is there any chance that these are caused by a faulty state of the project files due to the maxed out server disk or are they caused by the higher clock frequency IP designs?

Thank you all in advance.

 

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cloukas
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Registered: ‎12-16-2018

Hello @marcb and thank you for your response!

I have actually started a new project and repeated the exact same design there from scratch. This seems to have solved the problem, so it either was something I overlooked or it was a faulty project file build. I do not know if this will work for everyone though so I am not sure if I should post it as an answer.

 

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viviany
Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

So it fails at route_design, right?

Have you tried different strategies?

-vivian

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cloukas
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Registered: ‎12-16-2018

Like I wrote, changing strategies worked for a 200 MHz clock, but at 250 MHz, simply changing strategies did not work, and that is why I resynthesized my IPs for a higher clock frequency. That is where the problem showed up.

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marcb
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Registered: ‎05-08-2012

Hi @cloukas.

The BUFGCE_LEAF_* sites are physical locations, and Vivado looks to be having trouble with the connections within these. It might help to use successful build, as a reference for finding out what to change. One test would be to see what clocks are using those sites, and use the CLOCK_REGION constraint on this clock based o the successful version.

A better understanding might be gained by comparing the clocking information between the successful and failing builds with "report_clock_utilization -file clk_util.rpt -write_xdc clk_util_floorplan.xdc"

 

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cloukas
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Registered: ‎12-16-2018

Hello @marcb and thank you for your response!

I have actually started a new project and repeated the exact same design there from scratch. This seems to have solved the problem, so it either was something I overlooked or it was a faulty project file build. I do not know if this will work for everyone though so I am not sure if I should post it as an answer.

 

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rshekhaw
Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @cloukas ,

Glad to know issue is resolved. Please mark the post as accepted soution which resolved the issue and close the thread.

 

Thanks,
Raj

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