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Anonymous
Not applicable
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Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it

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I am working with Vivado 2014.4 . In the design I use a clock and I found that in the probe clock, instead of free running clock, the clock i have used turned up. Is this the reason for the issue.

 

These are the messages :

WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z020_1 and the probes file /home/divya/Desktop/GPS_IMU_2014_229/RDP_FIXED/project_dbg/project_dbg.runs/impl_3/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file OR
2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.

 

 

 

report_debug_core Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:48:31 MST 2014 | Date : Thu Sep 22 23:27:49 2016 | Host : divya-OptiPlex-7010 running 64-bit Ubuntu 14.04.5 LTS | Design : FIXED_INT_wrapper | Device : xc7z020clg484-1 | Speed File : -1 ------------------------------------------------------------------------------------ Debug Core Information Table of Contents ----------------- 1. Debug Cores 1.1 dbg_hub: (labtools_xsdbm_v1, black box, inserted) 1.2 u_ila_0: (labtools_ila_v5, black box, inserted) 1. Debug Cores -------------- 1.1 dbg_hub: (labtools_xsdbm_v1, black box, inserted) ----------------------------------------------------- Channel Data for Debug Core "dbg_hub" +---------------+---------+---------------+------------------+----------------------------------------+----------+------------+ | Port Name | Port | Port Spec | Channel Name | Net Name | Net Type | MARK_DEBUG | | | Type | | | | | | +---------------+---------+---------------+------------------+----------------------------------------+----------+------------+ | clk | input | clk | clk[0] | u_ila_0_FIXED_INT_PP_GPS_0_0_1_clk | signal | false | +---------------+---------+---------------+------------------+----------------------------------------+----------+------------+ 1.2 u_ila_0: (labtools_ila_v5, black box, inserted) --------------------------------------------------- Channel Data for Debug Core "u_ila_0" +---------------+---------+---------------+------------------+----------------------------------------+----------+------------+ | Port Name | Port | Port Spec | Channel Name | Net Name | Net Type | MARK_DEBUG | | | Type | | | | | | +---------------+---------+---------------+------------------+----------------------------------------+----------+------------+ | clk | input | clk | clk[0] | FIXED_INT_PP_GPS_0_0_1_clk | signal | false | +---------------+---------+---------------+------------------+----------------------------------------+----------+------------+ | probe0 | input | probe | probe0[0] | lattitude_deg_out[0] | signal | true | | | | | probe0[1] | lattitude_deg_out[1] | signal | true | | | | | probe0[2] | lattitude_deg_out[2] | signal | true | | | | | probe0[3] | lattitude_deg_out[3] | signal | true | | | | | probe0[4] | lattitude_deg_out[4] | signal | true | | | | | probe0[5] | lattitude_deg_out[5] | signal | true | | | | | probe0[6] | lattitude_deg_out[6] | signal | true | | | | | probe0[7] | lattitude_deg_out[7] | signal | true | | | | | probe0[8] | lattitude_deg_out[8] | signal | true | | | | | probe0[9] | lattitude_deg_out[9] | signal | true | | | | | probe0[10] | lattitude_deg_out[10] | signal | true | | | | | probe0[11] | lattitude_deg_out[11] | signal | true | | | | | probe0[12] | lattitude_deg_out[12] | signal | true | | | | | probe0[13] | lattitude_deg_out[13] | signal | true | | | | | probe0[14] | lattitude_deg_out[14] | signal | true | | | | | probe0[15] | lattitude_deg_out[15] | signal | true | | | | | probe0[16] | lattitude_deg_out[16] | signal | true | | | | | probe0[17] | lattitude_deg_out[17] | signal | true | | | | | probe0[18] | lattitude_deg_out[18] | signal | true | | | | | probe0[19] | lattitude_deg_out[19] | signal | true | | | | | probe0[20] | lattitude_deg_out[20] | signal | true | | | | | probe0[21] | lattitude_deg_out[21] | signal | true | | | | | probe0[22] | lattitude_deg_out[22] | signal | true | | | | | probe0[23] | lattitude_deg_out[23] | signal | true | | | | | probe0[24] | lattitude_deg_out[24] | signal | true | | | | | probe0[25] | lattitude_deg_out[25] | signal | true | | | | | probe0[26] | lattitude_deg_out[26] | signal | true | | | | | probe0[27] | lattitude_deg_out[27] | signal | true | | | | | probe0[28] | lattitude_deg_out[28] | signal | true | | | | | probe0[29] | lattitude_deg_out[29] | signal | true | | | | | probe0[30] | lattitude_deg_out[30] | signal | true | | | | | probe0[31] | lattitude_deg_out[31] | signal | true | +---------------+---------+---------------+------------------+----------------------------------------+----------+------------+ | probe1 | input | probe | probe1[0] | lattitude_min_out[0] | signal | true | | | | | probe1[1] | lattitude_min_out[1] | signal | true | | | | | probe1[2] | lattitude_min_out[2] | signal | true | | | | | probe1[3] | lattitude_min_out[3] | signal | true | | | | | probe1[4] | lattitude_min_out[4] | signal | true | | | | | probe1[5] | lattitude_min_out[5] | signal | true | | | | | probe1[6] | lattitude_min_out[6] | signal | true | | | | | probe1[7] | lattitude_min_out[7] | signal | true | | | | | probe1[8] | lattitude_min_out[8] | signal | true | | | | | probe1[9] | lattitude_min_out[9] | signal | true | | | | | probe1[10] | lattitude_min_out[10] | signal | true | | | | | probe1[11] | lattitude_min_out[11] | signal | true | | | | | probe1[12] | lattitude_min_out[12] | signal | true | | | | | probe1[13] | lattitude_min_out[13] | signal | true | | | | | probe1[14] | lattitude_min_out[14] | signal | true | | | | | probe1[15] | lattitude_min_out[15] | signal | true | | | | | probe1[16] | lattitude_min_out[16] | signal | true | | | | | probe1[17] | lattitude_min_out[17] | signal | true | | | | | probe1[18] | lattitude_min_out[18] | signal | true | | | | | probe1[19] | lattitude_min_out[19] | signal | true | | | | | probe1[20] | lattitude_min_out[20] | signal | true | | | | | probe1[21] | lattitude_min_out[21] | signal | true | | | | | probe1[22] | lattitude_min_out[22] | signal | true | | | | | probe1[23] | lattitude_min_out[23] | signal | true | | | | | probe1[24] | lattitude_min_out[24] | signal | true | | | | | probe1[25] | lattitude_min_out[25] | signal | true | | | | | probe1[26] | lattitude_min_out[26] | signal | true | | | | | probe1[27] | lattitude_min_out[27] | signal | true | | | | | probe1[28] | lattitude_min_out[28] | signal | true | | | | | probe1[29] | lattitude_min_out[29] | signal | true | | | | | probe1[30] | lattitude_min_out[30] | signal | true | | | | | probe1[31] | lattitude_min_out[31] | signal | true | +---------------+---------+---------------+------------------+----------------------------------------+----------+------------+ | probe2 | input | probe | probe2[0] | altitude[0] | signal | true | | | | | probe2[1] | altitude[1] | signal | true | | | | | probe2[2] | altitude[2] | signal | true | | | | | probe2[3] | altitude[3] | signal | true | | | | | probe2[4] | altitude[4] | signal | true | | | | | probe2[5] | altitude[5] | signal | true | | | | | probe2[6] | altitude[6] | signal | true | | | | | probe2[7] | altitude[7] | signal | true | | | | | probe2[8] | altitude[8] | signal | true | | | | | probe2[9] | altitude[9] | signal | true | | | | | probe2[10] | altitude[10] | signal | true | | | | | probe2[11] | altitude[11] | signal | true | | | | | probe2[12] | altitude[12] | signal | true | | | | | probe2[13] | altitude[13] | signal | true | | | | | probe2[14] | altitude[14] | signal | true | | | | | probe2[15] | altitude[15] | signal | true | | | | | probe2[16] | altitude[16] | signal | true | | | | | probe2[17] | altitude[17] | signal | true | | | | | probe2[18] | altitude[18] | signal | true | | | | | probe2[19] | altitude[19] | signal | true | | | | | probe2[20] | altitude[20] | signal | true | | | | | probe2[21] | altitude[21] | signal | true | | | | | probe2[22] | altitude[22] | signal | true | | | | | probe2[23] | altitude[23] | signal | true | | | | | probe2[24] | altitude[24] | signal | true | | | | | probe2[25] | altitude[25] | signal | true | | | | | probe2[26] | altitude[26] | signal | true | | | | | probe2[27] | altitude[27] | signal | true | | | | | probe2[28] | altitude[28] | signal | true | | | | | probe2[29] | altitude[29] | signal | true | | | | | probe2[30] | altitude[30] | signal | true | | | | | probe2[31] | altitude[31] | signal | true | +---------------+---------+---------------+------------------+----------------------------------------+----------+------------+

 

I have followed steps mentioned in https://forums.xilinx.com/t5/Design-Tools-Others/Hardware-Manager-finds-no-debug-cores/m-p/710113. still no result. Help me out in resolving the issue.

 

Divya

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vijayak
Xilinx Employee
Xilinx Employee
11,652 Views
Registered: ‎10-24-2013

Hi @Anonymous

 

Please check if this AR helps.

http://www.xilinx.com/support/answers/64764.html

Thanks,Vijay
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4 Replies
vijayak
Xilinx Employee
Xilinx Employee
11,653 Views
Registered: ‎10-24-2013

Hi @Anonymous

 

Please check if this AR helps.

http://www.xilinx.com/support/answers/64764.html

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

balkris
Xilinx Employee
Xilinx Employee
7,688 Views
Registered: ‎08-01-2008
https://forums.xilinx.com/t5/Design-Tools-Others/ILA-issues-with-Vivado-2014-3/td-p/539271
http://www.xilinx.com/support/answers/64764.html
https://forums.xilinx.com/t5/Debug-Tools/WARNING-Labtools-27-3123-The-debug-hub-core-was-not-detected-at/td-p/647081/page/2
Thanks and Regards
Balkrishan
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Anonymous
Not applicable
7,676 Views

Thanks,

 

Problem is due to ila core clock is not free running clock..

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Bluesky
Newbie
Newbie
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Registered: ‎07-18-2020

I encoutered the same problem and hope the solution can help you.

The problem in my project is: Vivado automatically connect the debug core clk to PS 的 FCLK_CLK0, which is not a free-run clock.

The clock is enabled after PS start. So that I try to open SDK and start PS in debug mode , after initialization, go back to Vivado, program device again,

the debug core can be detected succesfully. In my situation, it is the debug core clk cause the problem.

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