02-06-2020 07:11 AM
I created 2 FPGA builds on 2 different machines using Vivado 2017.4 running 2 different Linux OS using the same design.
Build 1: Using Linux Red Hat Enterprise Linux Server release 6.4; default maxThreads = 8; build time = ~4hrs; MET TIMING
Build 2: Using Ubuntu 18.04.3 LTS; default maxThreads = 8; build time = ~2hrs; FAILED TIMING
Reran both builds using maxThreads = 1, both resulted in similar error below:
An unrecoverable error has occurred, synthesis cancelled.
TclStackFree: incorrect freePtr. Call out of sequence?
Abnormal program termination (6)
Reran both builds using maxThreads = 1 and using vivado '-stack 2000' option, but similar termination.
Ran a third build using a different Linux OS using the following:
Build 3: Using Ubuntu 16.04.6 LTS; default maxThreads = 8; Results in: Abnormal program termination (6)
Any ideas on how to get passed this issue?
02-06-2020 12:24 PM
That's very curious - it implies to me that Vivado uses a seed for P&R, but the seed is different depending on something in the environment. However, Xilinx claims that Vivado doesn't use a seed, and uses some other (unspecified) heuristic that isn't seed-based. I'm not quite sure what that means - the unspecified heuristic must in some way be a seed, and presumably differs depending on the OS.
I suspect your only option is to choose the OS you want and change the strategy until you get something that works. Search for 'strategy' in UG901.
02-06-2020 12:49 PM
In the old ISE days, you were able to set the seed. With Vivado, in the first stage of the build, the checksums are already different. This is concerning in that if I have a design that build and meets timing using a certain OS, and if I ship this same design to another site and the other site builds the same design and then it does not meet timing....very concerning.
I might just have to modify my build script to just churn until it meets timing.
02-06-2020 12:57 PM
02-10-2020 06:45 AM
Some of the machine settings are as follows:
Build 1: MEETS TIMING; ~4hr build time; Intel(R) Xeon(R) CPU E5-4650 0 @ 2.70GHz; 4 CPUs with 8 cores/CPU; 512GB RAM
Build 2: FAILS TIMING; ~2hr build time; Intel(R) Core(TM) i7-4770 CPU @ 3.40GHz; 2 CPUs with 4 cores/CPU; 32GB RAM
Build 2 completes in less time but fails in timing.