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Observer
Observer
11,840 Views
Registered: ‎12-17-2014

Differential clock driving one IBUFGDS and one IBUFDS_GTE2

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I have a single differential clock as input in my design:

 

CLK_200M_P : in STD_LOGIC;
CLK_200M_N : in STD_LOGIC;

 

The differential signal is directly connected to a "IBUFDS_GTE2" and a "IBUFGDS".

Originaly, it gives me an error in the SYNTHESIS step.

but, If i disable the " -iobuf add I/O buffers" option in the synthesis, then it gives me an error in the MAP step.

 

Please indicate how can use the single differential clock to drive both buffers, thank you!

 

 

 

 

The error at SYNTHESIS step:

 

ERROR:Xst:2035 - Port <CLK_200M_P> has illegal connections. This port is connected to an input buffer and other components.
Input Buffer:
Port <I> of node <clkin1_buf> (IBUFGDS) in unit <clk_drp>
Other Components:
Port <I> of node <ibufds_instq0_clk1> (IBUFDS_GTE2) in unit <clocks>

 

The error at MAP step:

 

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
single IOB18 component because the site type selected is not compatible.

Further explanation:
Symbol "clocks/ibufds_instq0_clk1" is not a kind of symbol that can join an
IOB18 component.
Symbols involved:
IBUFDS_GTE2 symbol "clocks/ibufds_instq0_clk1" (Output Signal = refclk)
SlaveBuffer symbol "clocks/clk_drp/clkin1_buf/SLAVEBUF.DIFFIN" (Output
Signal = clocks/clk_drp/clkin1_buf/SLAVEBUF.DIFFIN)
PAD symbol "CLK_200M_N" (Pad Signal = CLK_200M_N)

 

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
single IOB18 component because the site type selected is not compatible.

Further explanation:
Symbol "clocks/ibufds_instq0_clk1" is not a kind of symbol that can join an
IOB18 component.
Symbols involved:
IBUFDS_GTE2 symbol "clocks/ibufds_instq0_clk1" (Output Signal = refclk)
DIFFAMP symbol "clocks/clk_drp/clkin1_buf/IBUFDS" (Output Signal =
clocks/clk_drp/clkin1)
PAD symbol "CLK_200M_P" (Pad Signal = CLK_200M_P)

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Explorer
Explorer
18,894 Views
Registered: ‎02-22-2010

Re: Differential clock driving one IBUFGDS and one IBUFDS_GTE2

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To clarify what is has been said:

 

Your 200MHz differential clock is input into (I assume) a clock capable IO site. This clock should be input to a IBUFGDS and will drive fabric logic.

 

It is NOT RECOMMENDED to use this clock as a reference clock for the GT transceiver.

 

If indeed you are using a GT, you will have to input a Reference Clock through its dedicated pins. In this case, the GT reference clock will be input to a IBUFDS_GTE. 

View solution in original post

5 Replies
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Moderator
Moderator
11,826 Views
Registered: ‎01-16-2013

Re: Differential clock driving one IBUFGDS and one IBUFDS_GTE2

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Hi,

Please refer below AR

http://www.xilinx.com/support/answers/25058.html
http://www.xilinx.com/support/answers/34270.html
http://www.xilinx.com/support/answers/31432.html

Also from your description it is clear that you are using diff clock so you must use IBUFGDS.

Thanks,
Yash
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Xilinx Employee
Xilinx Employee
11,822 Views
Registered: ‎09-20-2012

Re: Differential clock driving one IBUFGDS and one IBUFDS_GTE2

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Hi,

 

The clock input pad can drive only one input buffer either IBUFDS or IBUFDS_GTE2. 

 

The IBUFDS_GTE2 buffers are used to drive reference clock to GT. The inputs of this buffer has to be locked to GT dedicated ref clock pins. I guess you are using IBUFDS_GTE2 buffers and locking the ports to user IO pins hence there is MAP error.

 

If you are not using GT in your design then change the buffer to IBUFDS.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Highlighted
Explorer
Explorer
18,895 Views
Registered: ‎02-22-2010

Re: Differential clock driving one IBUFGDS and one IBUFDS_GTE2

Jump to solution

To clarify what is has been said:

 

Your 200MHz differential clock is input into (I assume) a clock capable IO site. This clock should be input to a IBUFGDS and will drive fabric logic.

 

It is NOT RECOMMENDED to use this clock as a reference clock for the GT transceiver.

 

If indeed you are using a GT, you will have to input a Reference Clock through its dedicated pins. In this case, the GT reference clock will be input to a IBUFDS_GTE. 

View solution in original post

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Observer
Observer
11,792 Views
Registered: ‎12-17-2014

Re: Differential clock driving one IBUFGDS and one IBUFDS_GTE2

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Yes, this is the case. 

I wanted to use the same clock as main clock for my design and as reference clock for a transceiver.

But, as I now understand, I need to have a dedicated reference clock for the transceiver.

 

Thank you for the reply.

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Scholar
Scholar
11,784 Views
Registered: ‎06-23-2013

Re: Differential clock driving one IBUFGDS and one IBUFDS_GTE2

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If your clock comes into the IBUFDS_GTE input pins, it can drive a GT transceiver quad (plus one quad north and south) and it can drive the rest of your design through a BUFG as well.