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Explorer
Explorer
1,021 Views
Registered: ‎03-31-2016

Disable BUFGCE issue

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Hello

I want to used vu440 FPGA device.

 

Have any constraint can be disable BUFGCE?

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: Disable BUFGCE issue

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@quincyq2003,

 

If you do not want the tool to infer any clock buffers (BUFGCE) then you can use clock_buffer_type set to None. 

set_property CLOCK_BUFFER_TYPE NONE [get_nets ]

 

Check page 156 in below UG:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug912-vivado-properties.pdf#page=156

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

1 Reply
Highlighted
Moderator
Moderator
1,410 Views
Registered: ‎01-16-2013

Re: Disable BUFGCE issue

Jump to solution

@quincyq2003,

 

If you do not want the tool to infer any clock buffers (BUFGCE) then you can use clock_buffer_type set to None. 

set_property CLOCK_BUFFER_TYPE NONE [get_nets ]

 

Check page 156 in below UG:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug912-vivado-properties.pdf#page=156

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post